Patents by Inventor Chia-Jen Hsu

Chia-Jen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10444067
    Abstract: An optical sensing apparatus including a light sensor, a plurality of light-emitting devices, and a controller is provided. The light sensor is disposed on a substrate. The light sensor senses a light reflection signal in a sensing area of the optical sensing apparatus. The light-emitting devices are disposed on the substrate and around the light sensor. The light-emitting devices provide an optical signal to be transmitted into the human tissue. Then, the optical signal is reflected by the human tissue to generate the light reflection signal. The controller determines whether the position of the human tissue has been changed in the sensing area. The controller drives at least one light-emitting device of the light-emitting devices and adjusts the light intensity thereof to provide the appropriate optical signal. Besides, a measuring method of the optical sensing apparatus is proposed.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: October 15, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Hao Hsu, Chun-Te Chuang, Chih-Jen Chen, Yu-Tang Shen
  • Patent number: 10432834
    Abstract: A lens driving module is provided, configured to drive an optical lens to move, including a holder, a casing, a base, an electromagnetic driving assembly and a glue. The optical lens is disposed in a receiving space of the holder. The holder is disposed between the casing and the base. The casing has a plastic material. The electromagnetic driving assembly for moving the holder is disposed between the holder and the casing. The base has a plurality of protrusions extending toward the casing, and each of the protrusions has a side surface. The glue is disposed between the side surfaces and the casing, wherein the side surfaces are parallel to the central axis of the optical lens.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 1, 2019
    Assignee: TDK Taiwan Corp.
    Inventors: Shou-Jen Liu, Chia-Pin Hsu, Shang-Yu Hsu, Sin-Jhong Song
  • Patent number: 10416533
    Abstract: A lens driving mechanism is provided for moving a lens unit along a light axis, including a frame, a base, a lens holder, and a driving assembly. The frame has plastic material and forms an opening. The base is in contact with and fixed to the frame, wherein a space is formed between the base and the frame. The lens holder is movably disposed in the space for holding the lens unit, wherein an external light enters the space through the opening to the lens unit. The driving assembly is disposed in the space and is connected to the lens holder and the frame, to impel the lens unit to move along the light axis.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: September 17, 2019
    Assignee: TDK Taiwan Corp.
    Inventors: Shang-Yu Hsu, Shou-Jen Liu, Chia-Pin Hsu
  • Patent number: 10408780
    Abstract: The present invention provides a structure of a gas sensor, comprising: a support, having a front side, a back side opposite to the front side, a cell region, and a peripheral region circling the cell region; a cavity, formed on the back side of the support in the cell region; a heater, disposed on the front side of the support covering the cavity; a sensing element, disposed on the heater; and a sealing layer, formed on the back side of the support covering inside the cavity.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 10, 2019
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chia-Wei Lee, Chang-Sheng Hsu, Chih-Fan Hu, Chin-Jen Cheng, Chang Hsin Wu
  • Patent number: 10388243
    Abstract: The driving system for driving a display panel includes a timing controller and a source driving circuit. The source driving circuit includes a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The plurality of shift registers are classified into a plurality of shift register series, among which a first shift register series includes a first shift register being as one end and a second shift register being as the other end, and a second shift register series includes a third shift register being as one end and a fourth shift register being as the other end. The timing controller is connected to the first shift register, the second shift register, the third shift register, and the fourth shift register, and transmits a first start pulse to the first shift register and a second start pulse to the third shift register.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: August 20, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Shu-Wei Chang, Chia-Chi Yu, Kuo-Jen Hsu
  • Publication number: 20190196322
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Publication number: 20190184157
    Abstract: An electrical stimulation control circuit including a pulse generator, a processing circuit and an electrode is provided. The pulse generator is configured to generate a switching signal. The processing circuit generates an energy signal according to the switching signal. The electrode is configured to contact the skin of a living body and includes a first comb electrode and a second comb electrode. The first comb electrode receives the energy signal and includes a plurality of first electrodes. The first electrodes are electrically connected to each other and extended along a first direction. The second comb electrode receives a ground signal and includes a plurality of second electrodes. The second electrodes are electrically connected to each other and extended along a second direction opposite to the first direction. The first electrodes and the second electrodes are arranged in a staggered manner and electrically insulated from each other.
    Type: Application
    Filed: December 28, 2017
    Publication date: June 20, 2019
    Inventors: Chia-Chan HSU, Chao-Jen HUANG, Su-Shin LEE
  • Publication number: 20190164786
    Abstract: An apparatus includes a substrate stage configured to secure a substrate thereon and a motion mechanism configured to rotate the substrate stage. The substrate stage includes a plurality of holding pins for holding an edge of the substrate. Rotating the substrate stage causes a chemical solution dispensed on an upper surface of the substrate to spread outwardly toward the edge of the substrate. At least one of the plurality of holding pins includes at least one opening or at least one tapered side surface, or both, for guiding the chemical solution to flow off the substrate.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 30, 2019
    Inventors: Chia-Lun Chen, Ming-Sung Hung, Po-Jen Shih, Wen-Hung Hsu
  • Publication number: 20190148110
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 16, 2019
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Publication number: 20180272565
    Abstract: Provided is a method of producing pellets of a graphene-polymer composite, the method comprising: (a) mixing multiple particles of a graphitic material and multiple particles of a solid polymer carrier material to form a mixture in an impacting chamber of an energy impacting apparatus; (b) operating the energy impacting apparatus with a frequency and an intensity for a length of time sufficient for peeling off graphene sheets from the graphitic material particles and transferring the graphene sheets to surfaces of the solid polymer carrier material particles to produce graphene-coated polymer particles inside the impacting chamber; and (c) feeding multiple graphene-coated polymer particles into an extruder to produce filaments of an extruded graphene-polymer composite and operating a cutter or pelletizer to cut the filaments into pellets of graphene-polymer composite. The process is fast (hours as opposed to days of conventional processes), environmentally benign, cost effective, and highly scalable.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 27, 2018
    Applicant: Nanotek Instruments, Inc.
    Inventors: Aruna Zhamu, Chia-Jen Hsu, Bor Z. Jang
  • Patent number: 9836420
    Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 5, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Dae Woon Kang, Desheng Ma, Derek Hing Sang Tam, Chia-Jen Hsu, Preeti Mulage
  • Patent number: 9727514
    Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: August 8, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Desheng Ma, Derek Hing Sang Tam, Chia-Jen Hsu, Preeti Mulage
  • Publication number: 20170202792
    Abstract: A method for treating a tau-associated disease is disclosed, which comprises the step of administering a pharmaceutical composition to a subject in need. Particularly, a method for treating Alzheimer's disease is disclosed, which comprises the step of administering a pharmaceutical composition to a subject in need.
    Type: Application
    Filed: August 16, 2016
    Publication date: July 20, 2017
    Inventors: Hsiu-Mei HSIEH, Ying-Chieh SUN, Guan-Chiun LEE, Guey-Jen LEE-CHEN, Ming-Tsan SU, Hui-Chen HUANG, Yu-Shao HSIEH, Chia-Jen HSU
  • Publication number: 20170104368
    Abstract: A wireless power receiver includes circuitry configured to receive a wirelessly induced voltage from a wireless power transmitter via a magnetically induced connection with the wireless power transmitter. It is determined that an overvoltage condition exists when the wirelessly induced voltage exceeds a threshold voltage, and the wirelessly induced voltage is reduced in response to determining that the overvoltage condition exists. The circuitry communicates the overvoltage condition to the wireless power transmitter via the magnetically induced connection while over-voltage protection is enabled.
    Type: Application
    Filed: September 15, 2016
    Publication date: April 13, 2017
    Applicant: BROADCOM CORPORATION
    Inventors: Russell E. RADKE, Ryan DESROSIERS, Chia-Jen HSU, Desheng MA
  • Publication number: 20160162430
    Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.
    Type: Application
    Filed: January 6, 2015
    Publication date: June 9, 2016
    Inventors: Desheng MA, Derek Hing Sang Tam, Chia-Jen Hsu, Preeti Mulage
  • Publication number: 20160162427
    Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.
    Type: Application
    Filed: March 11, 2015
    Publication date: June 9, 2016
    Inventors: Dae Woon KANG, Desheng MA, Derek Hing Sang TAM, Chia-Jen HSU, Preeti MULAGE
  • Patent number: 9356616
    Abstract: A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: May 31, 2016
    Assignee: Broadcom Corporation
    Inventors: Hui Pan, Xin Jin, Chia-Jen Hsu
  • Publication number: 20160093556
    Abstract: A quad-flat non-lead package structure includes a film layer, a conducting layer, a die, an encapsulant, and a plurality of metal bumps. The film layer has a plurality of through holes. A pad of the conducting layer and conducting wirings are disposed at the film layer but are not connected to each other. The conducting wirings are disposed at the through holes, respectively. The die is fixedly disposed at the pad and electrically connected to the conducting wirings. The encapsulant covers the conducting layer and the die. The metal bumps are disposed in the through holes, respectively, each have one end electrically connected to a corresponding one of the conducting wirings, and each have the other end protruding from a corresponding one of the through holes. Accordingly, the quad-flat non-lead package structure features reduced likelihood of pin disconnection and enhanced adhesiveness required for surface-mount technology.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 31, 2016
    Inventors: Ming-Te TU, Ching-I LIN, Chia-Jen HSU, Sheng-Jen LIN
  • Patent number: 9252833
    Abstract: Disclosed are various embodiments for providing a power-efficient driver architecture supporting rail-to-rail operation in full duplex mode. A driver is configured to drive a duplex signal over a transmission medium. A hybrid is configured to recover a received signal from the duplex signal. The received signal is generated by a remote transceiver. The driver is configured to drive the duplex signal based at least in part on the received signal recovered by the hybrid.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: February 2, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: Hui Pan, Yuan Yao, Joseph Aziz, Derek Tam, Xin Wang, Chia-Jen Hsu
  • Publication number: 20150279796
    Abstract: A method of manufacturing a quad-flat no-leads package (QFN) structure includes: forming a conducting layer on a surface of a thin-film layer; forming a plurality of conduction wirings from the conducting layer by a means of circuit layout; electrically connecting contact pads of a die to front ends of the conduction wirings, respectively; forming a plurality of through-holes in the thin-film layer by a means of drilling, such that terminal ends of the conduction wirings are exposed from the through-holes, respectively; and forming a plurality of metal bumps at the through-holes, respectively, such that signals from the die are sent to a bottom surface of the thin-film layer through the conduction wirings. Hence, the QFN structure and the method of manufacturing the same based on application of wafer-level chip-scale package (WLCSP) and extension of tape QFN to simplify the package manufacturing process, cut production costs, and enhance production yield.
    Type: Application
    Filed: June 17, 2014
    Publication date: October 1, 2015
    Inventors: Ming-Te TU, Ching-I LIN, Chia-Jen HSU, Sheng-Jen LIN