Abstract: An optical mechanism is provided, including a housing, a base, and a metal supporting member. The housing has a top cover and a sidewall connected to the top cover, wherein the top cover and the sidewall comprises plastic material. The base is connected to the housing, wherein an optical element is accommodated in a space between the housing and the base. At least a part of the metal supporting member is embedded in the housing.

Abstract: A semiconductor wafer cleaning apparatus is provided. The semiconductor wafer cleaning apparatus includes a spin base, a spindle extending through the spin base, and a clamping member covering the spin base. The spindle includes a mounting part and a supporting part disposed on the mounting part. The mounting part includes an inner projection, the supporting part includes a conical projection, and the conical projection is surrounded by the inner projection. The semiconductor wafer cleaning apparatus further includes a first sealing ring disposed between the spin base and the mounting part.

Abstract: A driving circuit, for driving a touch display panel, includes a controller, a first diode, a first capacitor, a second diode and a second capacitor. The controller is configured to provide a first modulation signal and a second modulation signal. The first diode is coupled between a power integrated circuit and a first node for providing a low gate output signal to the touch display panel. The first capacitor is coupled between the controller and the first node. The second diode is coupled between the power integrated circuit and a second node for providing a high gate output signal to the touch display panel. The second capacitor is coupled between the controller and the second node. During a touch period, the controller is configured to provide the first modulation signal with toggling voltage levels, and provide the second modulation signal with toggling voltage levels.

Abstract: A metal-insulator-metal (MIM) capacitor structure is provided. The MIM capacitor structure includes a first conductive layer formed over a substrate, and the first conductive layer includes a first portion and a second portion. The MIM capacitor structure also includes an insulating layer formed over the first portion of the first conductive layer and a second conductive layer formed over the first conductive layer. The second conductive layer includes a first portion and a second portion, the first portion of the second conductive layer is in direct contact with the insulating layer, and the second portion of the second conductive layer is in direct contact with the second portion of the first conductive layer.

Abstract: A metal-insulator-metal (MIM) capacitor structure is provided. The MIM capacitor structure includes a first conductive layer formed over a substrate, and the first conductive layer includes a first portion and a second portion. The MIM capacitor structure also includes an insulating layer formed over the first portion of the first conductive layer and a second conductive layer formed over the first conductive layer. The second conductive layer includes a first portion and a second portion, the first portion of the second conductive layer is in direct contact with the insulating layer, and the second portion of the second conductive layer is in direct contact with the second portion of the first conductive layer.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor structure is provided. The method includes providing a substrate and forming an interconnect structure over the substrate. The interconnect structure includes a top metal layer, and wherein the top metal layer includes a first portion and a second portion. The method includes forming an insulating layer on the first portion of the top metal layer; and forming a metal pad on the insulating layer. The metal pad includes a first portion and a second portion, the MIM capacitor is constructed by the first portion of the top metal layer, the insulating layer and the first portion of the metal pad, and the second portion of the metal pad directly contacts the first portion of the metal pad and the second portion of the top metal layer.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor structure is provided. The method includes providing a substrate and forming an interconnect structure over the substrate. The interconnect structure includes a top metal layer, and wherein the top metal layer includes a first portion and a second portion. The method includes forming an insulating layer on the first portion of the top metal layer; and forming a metal pad on the insulating layer. The metal pad includes a first portion and a second portion, the MIM capacitor is constructed by the first portion of the top metal layer, the insulating layer and the first portion of the metal pad, and the second portion of the metal pad directly contacts the first portion of the metal pad and the second portion of the top metal layer.

Abstract: Embodiments of mechanisms for forming a semiconductor device with metal-insulator-metal (MIM) capacitor structure are provided. The MIM capacitor structure includes a substrate; and a MIM capacitor formed on the substrate. The MIM capacitor includes a bottom electrode formed over the substrate. The bottom electrode is a top metal layer. The MIM capacitor also includes an insulating layer formed on the bottom electrode; and a top electrode formed on the insulating layer.

Abstract: An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the high-speed signal output pin are disposed on a package of the IC. The common node and the core circuit are disposed in the IC. The common node is directly and electrically coupled to the high-speed signal input pin. The high-speed signal output pin is directly and electrically coupled to the common node. A high-speed signal input terminal of the core circuit is directly and electrically coupled to the common node.

Abstract: Embodiments of mechanisms for forming a semiconductor device with metal-insulator-metal (MIM) capacitor structure are provided. The MIM capacitor structure includes a substrate; and a MIM capacitor formed on the substrate. The MIM capacitor includes a bottom electrode formed over the substrate. The bottom electrode is a top metal layer. The MIM capacitor also includes an insulating layer formed on the bottom electrode; and a top electrode formed on the insulating layer.

Abstract: An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the high-speed signal output pin are disposed on a package of the IC. The common node and the core circuit are disposed in the IC. The common node is directly and electrically coupled to the high-speed signal input pin. The high-speed signal output pin is directly and electrically coupled to the common node. A high-speed signal input terminal of the core circuit is directly and electrically coupled to the common node.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-FIN layers.

Abstract: Methods of Manufacturing a Nitride Trapping EEPROM Flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-FIN layers.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.