Patents by Inventor Chia-Ming Cheng

Chia-Ming Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9690458
    Abstract: An image viewing method includes: determining at least a first partial image corresponding to a portion of a first image directly selected from a plurality of images, and driving a display apparatus according to the first partial image; in accordance with a user interaction input, determining a second partial image corresponding to a portion of a second image directly selected from the images; and driving the display apparatus according to at least the second partial image. In one implementation, the first image and the second image are spatially correlated, and a field of view (FOV) of each of the first image and the second image is larger than an FOV of the display apparatus.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 27, 2017
    Assignee: MEDIATEK INC.
    Inventor: Chia-Ming Cheng
  • Patent number: 9640488
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 2, 2017
    Assignee: XINTEC INC.
    Inventors: Yi-Min Lin, Yi-Ming Chang, Shu-Ming Chang, Yen-Shih Ho, Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 9635270
    Abstract: A method for performing image control in an electronic device and an associated apparatus are provided, where the method may include the steps of: obtaining a specific image from a camera module of the electronic device, and obtaining a specific focus-related parameter corresponding to the specific image, wherein the specific focus-related parameter is related to focus control of the camera module; determining a specific resize parameter corresponding to the specific image according to a relationship between the specific resize parameter and the specific focus-related parameter; and performing a resize operation on the specific image according to the specific resize parameter, to control the specific image to be displayed in a quasi-scale-invariant manner.
    Type: Grant
    Filed: July 24, 2016
    Date of Patent: April 25, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Cheng, Po-Hao Huang, Yuan-Chung Lee
  • Patent number: 9620431
    Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: April 11, 2017
    Assignee: XINTEC INC.
    Inventors: Chia-Ming Cheng, Tsang-Yu Liu, Chi-Chang Liao, Yu-Lung Huang
  • Patent number: 9601460
    Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 21, 2017
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chia-Ming Cheng, Shu-Ming Chang, Tzu-Wen Tseng
  • Publication number: 20170040372
    Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first
    Type: Application
    Filed: August 2, 2016
    Publication date: February 9, 2017
    Inventors: Yen-Shih HO, Tsang-Yu LIU, Chia-Sheng LIN, Chia-Ming CHENG
  • Patent number: 9554113
    Abstract: A video frame processing method, which comprises: (a) capturing at least two video frames via a multi-view camera system comprising a plurality of cameras; (b) recording timestamps for each the video frame; (c) determining a major camera and a first sub camera out of the multi-view camera system, based on the timestamps, wherein the major camera captures a major video sequence comprising at least one major video frame, the first sub camera captures a video sequence of first view comprising at least one video frame of first view; (d) generating a first reference video frame of first view according to one first reference major video frame of the major video frames, which is at a reference timestamp corresponding to the first reference video frame of first view, and according to at least one the video frame of first view surrounding the reference timestamp; and (e) generating a multi-view video sequence comprising a first multi-view video frame, wherein the first multi-view video frame is generated based on the
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: January 24, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Cheng, Po-Hao Huang, Yuan-Chung Lee, Chung-Hung Tsai, Chi-Cheng Ju, Ding-Yun Chen, Cheng-Tsai Ho
  • Publication number: 20160337603
    Abstract: A method for performing image control in an electronic device and an associated apparatus are provided, where the method may include the steps of: obtaining a specific image from a camera module of the electronic device, and obtaining a specific focus-related parameter corresponding to the specific image, wherein the specific focus-related parameter is related to focus control of the camera module; determining a specific resize parameter corresponding to the specific image according to a relationship between the specific resize parameter and the specific focus-related parameter; and performing a resize operation on the specific image according to the specific resize parameter, to control the specific image to be displayed in a quasi-scale-invariant manner.
    Type: Application
    Filed: July 24, 2016
    Publication date: November 17, 2016
    Inventors: Chia-Ming Cheng, Po-Hao Huang, Yuan-Chung Lee
  • Patent number: 9426386
    Abstract: A method for performing preview control in an electronic device and an associated apparatus are provided, where the method may include the steps of: obtaining a specific preview image from a camera module of the electronic device, and obtaining a specific focus-related parameter corresponding to the specific preview image, wherein the specific focus-related parameter is related to focus control of the camera module; determining a specific resize parameter corresponding to the specific preview image according to a predetermined relationship between the specific resize parameter and the specific focus-related parameter; and performing a resize operation on the specific preview image according to the specific resize parameter, to control the specific preview image to be displayed in a quasi-scale-invariant manner with respect to a plurality of preview images.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: August 23, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chia-Ming Cheng, Po-Hao Huang, Yuan-Chung Lee
  • Publication number: 20160230861
    Abstract: A linear actuator includes an actuator including a housing, a power drive mounted at one end of the housing, a screw rod axially disposed in the housing, a connection member connected between the screw rod and the power drive, a sliding block threaded onto the screw rod, and a push rod affixed to the sliding block and extending out of the housing, and a resistance scale including a resistance substrate affixed to an inner wall of the housing at an inner bottom side and a electric brush affixed to a bottom side of the sliding block and kept in contact with the resistance substrate.
    Type: Application
    Filed: March 30, 2015
    Publication date: August 11, 2016
    Inventor: Chia-Ming Cheng
  • Publication number: 20160211297
    Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.
    Type: Application
    Filed: January 19, 2016
    Publication date: July 21, 2016
    Inventors: Tsang-Yu LIU, Chia-Ming CHENG
  • Publication number: 20160212357
    Abstract: A method for performing preview control in an electronic device and an associated apparatus are provided, where the method may include the steps of: obtaining a specific preview image from a camera module of the electronic device, and obtaining a specific focus-related parameter corresponding to the specific preview image, wherein the specific focus-related parameter is related to focus control of the camera module; determining a specific resize parameter corresponding to the specific preview image according to a predetermined relationship between the specific resize parameter and the specific focus-related parameter; and performing a resize operation on the specific preview image according to the specific resize parameter, to control the specific preview image to be displayed in a quasi-scale-invariant manner with respect to a plurality of preview images.
    Type: Application
    Filed: January 19, 2015
    Publication date: July 21, 2016
    Inventors: Chia-Ming Cheng, Po-Hao Huang, Yuan-Chung Lee
  • Patent number: 9373597
    Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 21, 2016
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Chia-Ming Cheng, Shu-Ming Chang
  • Patent number: 9349710
    Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: May 24, 2016
    Assignee: XINTEC INC.
    Inventors: Chien-Hui Chen, Tsang-Yu Liu, Chun-Wei Chang, Chia-Ming Cheng
  • Publication number: 20160141254
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.
    Type: Application
    Filed: January 27, 2016
    Publication date: May 19, 2016
    Inventors: Yi-Min LIN, Yi-Ming CHANG, Shu-Ming CHANG, Yen-Shih HO, Tsang-Yu LIU, Chia-Ming CHENG
  • Patent number: 9318461
    Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 19, 2016
    Assignee: XINTEC INC.
    Inventors: Chun-Wei Chang, Kuei-Wei Chen, Chia-Ming Cheng, Chia-Sheng Lin, Chien-Hui Chen, Tsang-Yu Liu
  • Patent number: 9317958
    Abstract: An auto-convergence system includes a disparity unit, a convergence unit and an active learning unit. The disparity unit performs a disparity analysis upon an input stereo image pair, and accordingly obtains a disparity distribution of the input stereo image pair. The convergence unit adjusts the input stereo image pair adaptively according to the disparity distribution and a learned convergence range, and accordingly generates an output stereo image pair for playback. The active learning unit actively learns a convergence range during playback of stereo image pairs, and accordingly determines the learned convergence range.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 19, 2016
    Assignee: MEDIATEK INC.
    Inventor: Chia-Ming Cheng
  • Patent number: 9275958
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 1, 2016
    Assignee: XINTEC INC.
    Inventors: Yi-Min Lin, Yi-Ming Chang, Shu-Ming Chang, Yen-Shih Ho, Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 9177862
    Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 3, 2015
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Hsin Kuan, Long-Sheng Yeou, Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 9165890
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 20, 2015
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Shih-Chin Chen, Yi-Ming Chang, Chien-Hui Chen, Chia-Ming Cheng, Wei-Luen Suen, Chen-Han Chiang