Patents by Inventor Chia-Ming Cheng

Chia-Ming Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8410599
    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 2, 2013
    Inventors: Baw-Ching Perng, Ying-Nan Wen, Shu-Ming Chang, Ching-Yu Ni, Yun-Jui Hsieh, Wei-Ming Chen, Chia-Lun Tsai, Chia-Ming Cheng
  • Patent number: 8399963
    Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: March 19, 2013
    Inventors: Chia-Lun Tsai, Tsang-Yu Liu, Chia-Ming Cheng
  • Publication number: 20130058561
    Abstract: A photographic system for generating photos is provided. The photographic system comprises a photo composition unit, and a photo synthesizer. The photo composition unit is capable of determining an extracted view from a three dimensional (3D) scene. The photo synthesizer, coupled to the photo composition unit, is capable of synthesizing an output photo according to the extracted view.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: MEDIATEK INC.
    Inventor: Chia-Ming Cheng
  • Patent number: 8384174
    Abstract: A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 26, 2013
    Inventors: Hsin-Chih Chiu, Chia-Ming Cheng, Chuan-Jin Shiu, Bai-Yao Lou
  • Patent number: 8362515
    Abstract: An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: January 29, 2013
    Inventors: Chia-Ming Cheng, Chien-Hung Liu
  • Publication number: 20120292744
    Abstract: An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 22, 2012
    Inventors: Tsang-Yu LIU, Chia-Sheng LIN, Chia-Ming CHENG, Po-Shen LIN
  • Patent number: 8295050
    Abstract: A dual CPU and its heat dissipating structure are applied to a heat dissipating module installed on a dual-CPU computer device, and CPUs are arranged alternately with each other on a motherboard, and the heat dissipating modules are installed at positions of the CPUs, such that the alternately arranged heat dissipating modules can prevent interferences by external cold air, and a heat source produced by the CPUs can be conducted and dissipated to the outside to prevent the heat source form remaining at the surrounding of the CPUs and related components installed on the motherboard to achieve an excellent heat dissipating efficiency.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 23, 2012
    Assignee: Portwell Inc.
    Inventors: Hui-Hsuan Chuang, Chia-Ming Cheng
  • Publication number: 20120113587
    Abstract: A dual CPU and its heat dissipating structure are applied to a heat dissipating module installed on a dual-CPU computer device, and CPUs are arranged alternately with each other on a motherboard, and the heat dissipating modules are installed at positions of the CPUs, such that the alternately arranged heat dissipating modules can prevent interferences by external cold air, and a heat source produced by the CPUs can be conducted and dissipated to the outside to prevent the heat source form remaining at the surrounding of the CPUs and related components installed on the motherboard to achieve an excellent heat dissipating efficiency.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Inventors: Hui-Hsuan CHUANG, Chia-Ming Cheng
  • Publication number: 20120097999
    Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer located on the second surface of the substrate, wherein the protection layer has an opening; a light shielding layer located on the second surface of the substrate, wherein a portion of the light shielding layer extends into the opening of the protection layer; a conducting bump disposed on the second surface of the substrate and filled in the opening of the protection layer; and a conducting layer located between the substrate and the protection layer, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 26, 2012
    Inventors: Hsin-Chih CHIU, Chia-Ming CHENG, Chuan-Jin SHIU, Bai-Yao LOU
  • Publication number: 20110291139
    Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optical device disposed on the first surface; a conducting pad disposed on the first surface; a first alignment mark formed on the first surface; and a light shielding layer disposed on the second surface and having a second alignment mark, wherein the second alignment mark corresponds to the first alignment mark.
    Type: Application
    Filed: May 24, 2011
    Publication date: December 1, 2011
    Inventors: Hsin-Chih CHIU, Chia-Ming Cheng, Chuan-Jin SHIU, Bai-Yao LOU
  • Publication number: 20110248310
    Abstract: An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 13, 2011
    Inventors: Chia-Ming CHENG, Chien-Hung Liu
  • Publication number: 20110233770
    Abstract: A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Inventors: Hsin-Chih CHIU, Chia-Ming Cheng, Chuan-Jin Shiu, Bai-Yao Lou
  • Publication number: 20110227210
    Abstract: An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 22, 2011
    Inventor: Chia-Ming CHENG
  • Publication number: 20110156191
    Abstract: The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.
    Type: Application
    Filed: December 30, 2010
    Publication date: June 30, 2011
    Inventors: Ta-Hsuan LIN, Chuan-Jin SHIU, Chia-Ming CHENG, Tsang-Yu LIU
  • Publication number: 20110140267
    Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
    Type: Application
    Filed: August 3, 2010
    Publication date: June 16, 2011
    Inventors: Chia-Lun TSAI, Ching-Yu Ni, Tien-Hao Huang, Chia-Ming Cheng, Wen-Cheng Chien, Nan-Chun Lin, Wei-Ming Chen, Shu-Ming Chang, Bai-Yao Lou
  • Publication number: 20110127666
    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.
    Type: Application
    Filed: August 12, 2010
    Publication date: June 2, 2011
    Inventors: Chia-Lun TSAI, Chia-Ming CHENG, Long-Sheng YEOU
  • Publication number: 20110127681
    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 2, 2011
    Inventors: Ching-Yu NI, Chia-Ming Cheng, Nan-Chun Lin
  • Publication number: 20110128354
    Abstract: Systems and methods for obtaining camera parameters from images are provided. First, a sequence of original images associated with a target object under circular motion is obtained. Then, a background image and a foreground image corresponding to the target object within each original image are segmented. Next, shadow detection is performed for the target object within each original image. A first threshold and a second threshold are respectively determined according to the corresponding background and foreground images. Each original image, the corresponding background image, the first and second threshold are used for obtaining silhouette data and feature information associated with the target object within each original image. At least one camera parameter is obtained based on the entire feature information and the geometry of circular motion.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 2, 2011
    Inventors: Tzu-Chieh TIEN, Po-Hao Huang, Chia-Ming Cheng, Hao-Liang Yang, Hsiao-Wei Chen, Shang-Hong Lai, Susan Dong, Cheng-Da Liu, Te-Lu Tsai, Jung-Hsin Hsiao
  • Publication number: 20110079892
    Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 7, 2011
    Inventors: Chia-Lun Tsai, Tsang-Yu Liu, Chia-Ming Cheng
  • Publication number: 20100289092
    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat
    Type: Application
    Filed: April 8, 2010
    Publication date: November 18, 2010
    Inventors: Baw-Ching PERNG, Ying-Nan Wen, Shu-Ming Chang, Ching-Yu Ni, Yun-Jui Hsieh, Wei-Ming Chen, Chia-Lun Tsai, Chia-Ming Cheng