Patents by Inventor Chia-Ming Liu

Chia-Ming Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367632
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20220367102
    Abstract: A common mode choke is provided, including a hollow ferrite core, a plurality of coils wound around the ferrite core, and a substrate. Each of the coils has a first end and a second end. The substrate is disposed on the side of the ferrite core and has a plurality of through holes. The first and second ends of the coils are engaged in the through holes. When viewed along the central axis of the ferrite core, the first and second ends of the coils are located on the outer side the ferrite core.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 17, 2022
    Inventors: Chia-Ming LIU, Wen-Yu HUANG, Lei REN, Rui-Guang LIU
  • Publication number: 20220359754
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 10, 2022
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Patent number: 11495687
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Publication number: 20220346594
    Abstract: A portable stove with stabilized gas pressure has a valve assembly, a gas pressure stabilizer, and a burner. The valve assembly has a body and a valve core. The body has an inlet, an outlet, and a cavity. The valve core is received in the cavity and blocks the inlet and the outlet. The gas pressure stabilizer has a flexible membrane, a pushing assembly, a spindle, and a compression spring. The membrane is configured to isolate the cavity from the outlet. The pushing assembly is mounted on a center of the membrane and abuts the valve core. The spindle has is screwed on the body, and is movable along an axial direction. The compression spring is located in the body, abuts against the spindle and the pushing assembly, and is compressible along the axial direction. The burner is connected with the body.
    Type: Application
    Filed: June 21, 2021
    Publication date: November 3, 2022
    Inventor: Chia Ming Liu
  • Publication number: 20220328627
    Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.
    Type: Application
    Filed: August 16, 2021
    Publication date: October 13, 2022
    Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
  • Publication number: 20220328502
    Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.
    Type: Application
    Filed: December 30, 2021
    Publication date: October 13, 2022
    Inventors: Chia-Ta Yu, Chia-En Huang, Yi-Ching Liu, Yih Wang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20220320320
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
  • Patent number: 11462639
    Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Pan, Chia-Ta Hsieh, Po-Wei Liu, Yun-Chi Wu
  • Patent number: 11450741
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20220285382
    Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Publication number: 20220279968
    Abstract: A barbecue grill has a body, a barbecue grid, a heating device, a heating adjustment unit, a thermal sensor, and a control device. The heating adjustment unit is connected with the heating device. The thermal sensor is mounted in the body and detects an actual temperature. The control device has a constant temperature control module electrically connected to the heating adjustment unit and the thermal sensor. The constant temperature control module controls the heating adjustment unit to adjust heat output of the heating device according to a difference value between a target temperature and the actual temperature. The heat output of the heating device is increased or decreased according to the difference value to keep the temperature constant at the position of the thermal sensor.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 8, 2022
    Inventor: CHIA MING LIU
  • Patent number: 11424383
    Abstract: A semiconductor device includes: a first semiconductor region; and a first electrode on the first semiconductor region; wherein first semiconductor region includes a first layer and a second layer, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion has a first thickness, the second portion has a second thickness less than the first thickness, the first layer includes a first material and a first dopant, the first material includes multiple elements, the first dopant has a first concentration, the second layer includes a second material and a second dopant, the second material includes multiple elements, the second dopant has a second concentration, one of the elements of the first material of the first layer is different from the elements of the second material of the second layer.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 23, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hu, Wei-Chieh Lien, Chen Ou, Chia-Ming Liu, Tzu-Yi Chi
  • Patent number: 11417520
    Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Publication number: 20220255328
    Abstract: An electronic system includes a first device and a second device is provided. The first device includes a power connector, a first connector, a first battery, and a charging controller. The second device includes a second connector and a second battery. The power connector is configured to receive an external voltage. The first battery is electrically connected to the power connector and the first connector. The charging controller is electrically connected to the power connector and the first battery. The second connector is utilized for connecting the first connector. The second battery is electrically connected to the second connector. When the first connector is connected to the second connector, the charging controller selectively connects the first battery and the second battery in a series via the first connector and the second connector according to the level of the first battery and the second battery.
    Type: Application
    Filed: January 21, 2022
    Publication date: August 11, 2022
    Inventors: Chia Jui SHIH, Kai-Chun LIANG, Chia Yu LIU, Kian-Ming CHEE, Yii-Lin WU
  • Publication number: 20220233799
    Abstract: A ventilator-weaning timing prediction system, a program product therefor, and methods for building and using the same are disclosed to help a physician to determine a timing for a ventilator-using patient to try to weaning or completely wean from mechanical ventilation using AI-based prediction.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Jhi-Joung Wang, Hung-Jung Lin, Kuo-Chen Cheng, Shian-Chin Ko, Chin-Ming Chen, Shu-Chen Hsing, Mei-Yi Sung, Chung-Feng Liu, Chia-Jung Chen
  • Patent number: 11393926
    Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Publication number: 20220204375
    Abstract: Provided are a system and a method of treating wastewater. The system includes a forward osmosis (FO) liquid concentration apparatus and an electrodialysis (ED) apparatus. The FO liquid concentration apparatus increases the concentration of the salt in the wastewater to between 7% and 14%. The ED apparatus is disposed downstream of the FO liquid concentration apparatus and coupled to the FO liquid concentration apparatus to receive the wastewater introduced by the FO liquid concentration apparatus, and make the salt in the wastewater into an acid solution and a basic solution.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Hua Ho, David Chiuni Wang, Tsui-Jung Yang, Sin-Yi Huang, Yi-Fong Pan, Po-I Liu, Guan-You Lin, Ren-Yang Horng, Teh-Ming Liang
  • Patent number: 11374114
    Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Patent number: 11305971
    Abstract: A lifting device includes a guide unit, a support unit and a lifting unit. The guide unit is extendable and retractable along a direction. The support unit is disposed in the guide unit and includes a securing connector fixed to a seat body and made of elastic material, a support tube connected to the securing connector, and a support member disposed on the support tube. The lifting unit includes a first rod-actuating screw member disposed on the support member and having a first threaded hole, and a threaded rod unit including a first threaded rod extending into the support tube and being threadedly engaged with the first threaded hole, such that the first threaded rod is rotatable by an external force and movable in the direction.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: April 19, 2022
    Inventor: Chia-Ming Liu