Patents by Inventor Chia-Wei Cheng

Chia-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200147018
    Abstract: The present invention provides compositions comprising ?-hydroxybutyrate, cyclic or linear ?-hydroxybutyrate oligomers, and/or ?-hydroxybutyrate ester derivatives, or pharmaceutically-acceptable salts thereof. In various embodiments, the compositions are encapsulated by nanoparticles, such as nanoparticles comprising, e.g., poly(lactic-co-glycolic acid). In additional embodiments, the invention provides methods of using such compositions to induce intestinal stem cell regeneration and/or treat radiation-induced intestinal damage in a subject.
    Type: Application
    Filed: October 16, 2019
    Publication date: May 14, 2020
    Inventors: Omer Yilmaz, Chia-Wei Cheng, George Eng, Fang Wang
  • Patent number: 10651040
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 12, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20200117155
    Abstract: A shot peening valve controller comprises a hub connector configurable for connecting or operating one or more shot peening valve; a microprocessor that is connected to the hub connector; and a human-machine interface that is connected to the microprocessor. The human-machine interface is configured to operate the one or more shot peening valves respectively.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 16, 2020
    Inventors: Chia Loon CHENG, Chong Wei LEE, Keng Huat TAN, Ser Hean TAN
  • Publication number: 20200111737
    Abstract: A chip package includes a substrate, first and second dielectric layers, first and second metal layers, and first conductive vias. The first dielectric layer is on a bottom surface of the substrate. The first metal layer is on a bottom surface of the first dielectric layer. The first metal layer has first sections, and every two adjacent first sections have a gap therebetween. The second dielectric layer is on a bottom surface of the first metal layer and the bottom surface of the first dielectric layer. The second metal layer is on a bottom surface of the second dielectric layer, and has second sections respectively aligned with the gaps. Two sides of the second section respectively overlap two adjacent first sections. The first conductive via is in the second dielectric layer and in electrical contact with the first and second sections.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 9, 2020
    Inventors: Kuei-Wei CHEN, Chia-Ming CHENG
  • Publication number: 20200105580
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Application
    Filed: September 3, 2019
    Publication date: April 2, 2020
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • Publication number: 20200105668
    Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.
    Type: Application
    Filed: July 29, 2019
    Publication date: April 2, 2020
    Inventors: Chia-Wei Ho, Chun-Wei Hsu, Chi-Hsiang Shen, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20200105693
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Publication number: 20200098590
    Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-hsiang Shen, Chia-Wei Ho, Yang-chun Cheng
  • Publication number: 20200098811
    Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Inventors: Kuei-Wei CHEN, Chia-Ming CHENG, Chia-Sheng LIN
  • Publication number: 20200098591
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Application
    Filed: May 1, 2019
    Publication date: March 26, 2020
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Publication number: 20200073045
    Abstract: A display device having a display region and a peripheral region surrounding the display region is provided. The display device includes a first adhesion layer sandwiched between a display unit and a protective structure. The protective structure includes a first protective layer having a first length in a first direction. The protective structure also includes a second adhesion layer disposed on the first protective layer. The protective structure further includes a second protective layer disposed on the second adhesion layer, and the second protective layer has a second length in the first direction, wherein the difference between the first length and the second length is between 0 and 1 mm, and wherein the second protective layer is on the outermost side of the display device.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Inventors: I-Chang LIANG, I-Jung LIN, Yuan-Jen CHENG, Tsu-Hsien KU, Ying-Yao TANG, Fang-Cheng JHOU, Li-Chi LUO, Ruei-Ting HUANG, Chia-Wei LAI
  • Publication number: 20200074919
    Abstract: A pixel circuit applied to an uLED display including a LED, a first transistor╦ťa sixth transistor and a capacitor. The LED is coupled between a first voltage and a first node. The first transistor is coupled between the first node and a second node. The second transistor is coupled between the second node and a second voltage lower than the first voltage. The third transistor is coupled between a third voltage and a third node. The fourth transistor is coupled between the third node and a fourth node. The fifth transistor is coupled between the fourth node and a fourth voltage. A terminal of the sixth transistor is coupled to the first node. The capacitor is coupled between the second node and the fourth node. The fourth transistor is controlled by a second control signal. The third transistor, the fifth transistor and the sixth transistor are controlled by a third control signal.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: CHIA-CHE HUNG, MAO-HSUN CHENG, CHEN-CHI LIN, MENG-XI CHAN, TING-WEI GUO, PENG-BO XI
  • Publication number: 20200058595
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Yi CHEN, Jia-Hong CHU, Chi-Wen LAI, Chia-Ching LIANG, Kai-Hsiung CHEN, Yu-Ching WANG, Po-Chung CHENG, Hsin-Chin LIN, Meng-Wei CHEN, Kuei-Shun CHEN
  • Publication number: 20200050725
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Publication number: 20200051858
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Publication number: 20200029614
    Abstract: A method of alleviating symptoms of, or treating, pancreatic beta-cell damage in a subject includes a step of identifying a subject having pancreatic beta-cell damage. Multiple cycles of a diet protocol are administered to the subject. The diet protocol includes administering of a fasting mimicking diet and a re-feeding diet where the fasting mimicking diet is provided for a first time period and the re-feeding diet is provided for a second time period.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Valter D. LONGO, Chia-Wei Cheng
  • Patent number: 10542504
    Abstract: A wireless communication system and method is provided. The wireless communication system includes a wireless transceiver device and a processing device. The processing device includes a direction control module, a power adjusting module and a boundary setting module. The direction control module controls the scanning direction and generates a point direction information record according to each reference position respectively. The power adjusting module adjusts the transmitting power and generates a point power information record according to each reference position and the corresponding point direction information record respectively. The boundary setting module generates a boundary information record. The processing device controls the transmitting direction and the transmitting power according to the point direction information record(s), the point power information record(s) and the boundary information record, so as to limit a transmission of the wireless signal within a specific area.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 21, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yin-Chang Liu, Hsuan-Lin Cheng, Chih-Wei Wang, Chun-Yi Lu, Ya-Chen Chuang, Chia-Yu Chen, Tsung-Han Tsai
  • Patent number: 10515915
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Patent number: 10509881
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10502887
    Abstract: A display device having a display region and a peripheral region surrounding the display region is provided. The display device includes a first adhesion layer sandwiched between a display unit and a protective structure. The protective structure includes a first protective layer having a first length in a first direction. The protective structure also includes a second adhesion layer disposed on the first protective layer. The protective structure further includes a second protective layer disposed on the second adhesion layer, and the second protective layer has a second length in the first direction, wherein the difference between the first length and the second length is between 0 and 1 mm, and wherein the second protective layer is on the outermost side of the display device.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 10, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: I-Chang Liang, I-Jung Lin, Yuan-Jen Cheng, Tsu-Hsien Ku, Ying-Yao Tang, Fang-Cheng Jhou, Li-Chi Luo, Ruei-Ting Huang, Chia-Wei Lai