Patents by Inventor Chia Wen Liu

Chia Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170117377
    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.
    Type: Application
    Filed: January 9, 2017
    Publication date: April 27, 2017
    Inventors: Jean-Pierre Colinge, Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 9634132
    Abstract: A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions. The nanowire structure has a first band gap energy section joined with a second band gap energy section. The first band gap energy section is coupled to the source region and has a band gap energy level greater than the band gap energy level of the second band gap energy section. The second band gap energy section is coupled to the drain region. The first band gap energy section comprises a first material and the second band gap energy section comprises a second material wherein the first material is different from the second material. The semiconductor device further comprises a gate region around the junction between the first band gap energy section and the second band gap energy section.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Jean-Pierre Colinge
  • Patent number: 9620591
    Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Jean-Pierre Colinge
  • Publication number: 20170047429
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Application
    Filed: October 31, 2016
    Publication date: February 16, 2017
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu
  • Patent number: 9564431
    Abstract: A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a drain region. The semiconductor structure further comprises a metal gate that surrounds a portion of the vertical channel structure. The metal gate has a gate length. The metal gate has a first gate section with a first workfunction and a first thickness. The metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness level is different from the second thickness level and the sum of the first thickness level and the second thickness level is equal to the gate length. The ratio of the first thickness level to the second thickness level for the gate length was chosen to achieve a threshold voltage level for the semiconductor device.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 9536746
    Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeh Hsu, Chia-Wen Liu, Tsung-Hsing Yu, Ken-Ichi Goto, Shih-Syuan Huang
  • Patent number: 9525031
    Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Ken-Ichi Goto, Chia-Wen Liu, Yeh Hsu
  • Patent number: 9484460
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Carlos H. Diaz
  • Publication number: 20160064560
    Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
  • Publication number: 20160049472
    Abstract: A semiconductor device includes a nanowire structure and a stressor. The nanowire structure includes a first channel section and a second channel section. The stressor subjects the first channel section to a first strain level and the second channel section to a second strain level greater than the first strain level. The difference between the second strain level and the first strain level is less than the second strain level.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 18, 2016
    Inventors: TSUNG-HSING YU, YEH HSU, CHIA-WEN LIU, JEAN-PIERRE COLINGE
  • Patent number: 9236445
    Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Meikei Ieong, Ken-Ichi Goto, Zhiqiang Wu
  • Publication number: 20160005863
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: SHIN-JIUN KUANG, TSUNG-HSING YU, YI-MING SHEU, CHUN-YI LEE, CHIA-WEN LIU
  • Patent number: 9224814
    Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 9196730
    Abstract: A semiconductor device with variable channel strain is provided. The semiconductor device comprises a nanowire structure formed as a channel between a source region and a drain region. The nanowire structure has a first channel section subjected to a first strain level and joined with a second channel section subjected to a second strain level different from the first strain level. The first channel section is coupled adjacent to the drain region and the second channel section is coupled adjacent to the source region. The semiconductor device further comprises a gate region that has a first strain section and a second strain section. The first strain section is configured to cause the first channel section to be subjected to the first strain level and the second strain section is configured to cause the second channel section to be subjected to the second strain level.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: November 24, 2015
    Assignee: Taiwan Seminconductor Manufacturing Company Limited
    Inventors: Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Jean-Pierre Colinge
  • Publication number: 20150303302
    Abstract: A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a channel in a semiconductor composite. The active area includes a first active area layer having a first dopant concentration, a second active area layer having a second dopant concentration over the first active area layer, and a third active area layer having a third dopant concentration, over the second active area. The third dopant concentration is greater than the second dopant concentration, and the second dopant concentration is greater than the first dopant concentration. The channel includes a second channel layer comprising carbon over a first channel layer and a third channel layer over the second channel layer. The active area configuration improves drive current and reduces contact resistance, and the channel configuration increases short channel control, as compared to a semiconductor device without the active area and channel configuration.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Ken-Ichi Goto
  • Patent number: 9161943
    Abstract: A sustained release composition comprising a polymer and manufacturing method thereof. The sustained release composition comprises a polymer, a bioactive agent, and a release rate determined agent, wherein the release rate determined agent is dispersed in the sustained release composition to control the release rate of the bioactive agent. The method comprises providing an oil phase comprising a bioactive agent, a polymer, and a release rate determined agent; providing an aqueous phase comprising a surfactant; mixing the oil phase with the aqueous phase to form the sustained release composition having a controlled release effect.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 20, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jui-Mei Lu, Chia-Wen Liu, Po Hong Lai, John Jianghann Lin, Chiao Pin Li, Sung En Chen, Yo Wen Lo, Ming-Thau Sheu, Min-Ying Lin
  • Publication number: 20150263096
    Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Inventors: Tsung-Hsing Yu, Ken-Ichi Goto, Chia-Wen Liu, Yeh Hsu
  • Publication number: 20150263171
    Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Inventors: Yeh Hsu, Chia-Wen Liu, Tsung-Hsing Yu, Ken-Ichi Goto, Shih-Syuan Huang
  • Publication number: 20150249141
    Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Application
    Filed: March 30, 2015
    Publication date: September 3, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsing YU, Chia-Wen LIU, Ken-Ichi GOTO
  • Publication number: 20150236145
    Abstract: A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions. The nanowire structure has a first band gap energy section joined with a second band gap energy section. The first band gap energy section is coupled to the source region and has a band gap energy level greater than the band gap energy level of the second band gap energy section. The second band gap energy section is coupled to the drain region. The first band gap energy section comprises a first material and the second band gap energy section comprises a second material wherein the first material is different from the second material. The semiconductor device further comprises a gate region around the junction between the first band gap energy section and the second band gap energy section.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TSUNG-HSING YU, CHIA-WEN LIU, YEH HSU, JEAN-PIERRE COLINGE