Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297870
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 21, 2019
    Assignee: AMBRI INC.
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Publication number: 20190148450
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Patent number: 10276376
    Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20190122936
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10256096
    Abstract: A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Publication number: 20190051536
    Abstract: In some embodiments, the disclosure relates to an integrated circuit structure. The integrated circuit structure has a substrate and a first hard mask layer over the substrate. An island of a second hard mask layer is arranged on the first hard mask layer and is set back from sidewalls of the first hard mask layer. A sacrificial mask is disposed over the island of the second hard mask layer. The sacrificial mask has sidewalls that define an opening exposing upper surfaces of the first hard mask layer and the island of the second hard mask layer. The island of the second hard mask layer extends from below the sacrificial mask to laterally past the sidewalls of the sacrificial mask.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20190051523
    Abstract: The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10163723
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10109486
    Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10109497
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions that include a part of the second mask layer remaining after patterning. A mandrel is formed directly over the first mask layer after patterning the second mask layer. The first mask layer is etched according to a sacrificial mask formed using the mandrel and according to the cut regions to form a patterned first mask. The cut regions extend from within the sacrificial mask to laterally past sidewalls of the sacrificial mask. The substrate is processed according to the patterned first mask.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20180267046
    Abstract: Disclosed is a method for identifying a subject at risk of developing a recurrent or metastatic cancer, comprising detecting PD-L1+ circulating tumor cells in a blood sample, a tissue fluid sample or a specimen of the subject. Also disclosed is method for treating a cancer comprising identifying a subject having one ore more PD-L1+ circulating tumor cells by detecting PD-L1+ circulating tumor cells in a blood sample, a tissue fluid sample or a specimen of the subject, and administering a treatment to the subject.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Applicant: MiCareo Taiwan Co., Ltd.
    Inventors: Ju-Yu Tseng, Yen-Ru Chen, Chia-Ying Lee, Li-Fan Wu, Shin-Hang Wang, Jui-Lin Chen, Chwen-Cheng Chen
  • Publication number: 20180159179
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Application
    Filed: December 8, 2017
    Publication date: June 7, 2018
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Publication number: 20180090726
    Abstract: The disclosure provides seals for devices that operate at elevated temperatures and have reactive metal vapors, such as lithium, sodium or magnesium. In some examples, such devices include energy storage devices that may be used within an electrical power grid or as part of a standalone system. The energy storage devices may be charged from an electricity production source for later discharge, such as when there is a demand for electrical energy consumption.
    Type: Application
    Filed: August 30, 2017
    Publication date: March 29, 2018
    Inventors: Greg Thompson, David J. Bradwell, Vimal Pujari, Chia-Ying Lee, David McCleary, Jennifer Cocking, James D. Fritz
  • Patent number: 9911661
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9876258
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: January 23, 2018
    Assignee: AMBRI INC.
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Patent number: D821547
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 26, 2018
    Assignee: KOHLER (CHINA) INVESTMENT CO., LTD.
    Inventors: Jimin Niu, Chia Ying Lee, Lun Cheak Tan
  • Patent number: D828906
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 18, 2018
    Assignee: KOHLER CHINA INVESTMENT CO. LTD.
    Inventors: Tsung-Yu Lu, Chia-Ying Lee, Lun Cheak Tan
  • Patent number: D833576
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Kohler (China) Investment Co., Ltd
    Inventors: Chia-Ying Lee, Manki Yoo, Jimin Niu
  • Patent number: D833580
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: November 13, 2018
    Assignee: KOHLER(CHINA) INVESTMENT CO., LTD.
    Inventors: Jimin Niu, Chia Ying Lee, Lun Cheak Tan
  • Patent number: D849194
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 21, 2019
    Assignee: KOHLER CHINA INVESTMENT CO. LTD.
    Inventors: Tsung-Yu Lu, Chia-Ying Lee, Lun Cheak Tan