Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8987142
    Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 8962484
    Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 8962432
    Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20150047891
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20150015210
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Application
    Filed: May 23, 2014
    Publication date: January 15, 2015
    Applicant: Ambri, Inc.
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Publication number: 20140377962
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.
    Type: Application
    Filed: September 8, 2014
    Publication date: December 25, 2014
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 8865600
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. Accordingly, first patterned second hard mask (HM) region is patterned, thus forming the line end space structure associated with an end-to-end space.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 8850369
    Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Hsiang Lung, Kuei-Shun Chen, Meng-Wei Chen, Chia-Ying Lee
  • Patent number: 8841214
    Abstract: A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20140273433
    Abstract: Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible.
    Type: Application
    Filed: June 18, 2013
    Publication date: September 18, 2014
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20140273442
    Abstract: A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout.
    Type: Application
    Filed: November 15, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Shih-Ming Chang, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau, Chia-Ying Lee, Jyu-Horng Shieh, Chung-Ju Lee, Cheng-Hsiung Tsai, Tien-I Bao, Shau-Lin Shue
  • Patent number: 8828885
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 8800073
    Abstract: A surround for use in a bath or a shower has a back and a side. The side has a protrusion extending therefrom. An open shelf attaches to either the back or the side. The protrusion at least partially restricts a view of the shelf.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 12, 2014
    Assignee: Masco Corporation of Indiana
    Inventors: Victor Hoernig, Geraint Krumpe, Manki Yoo, Andrew Mercidita, Angela Biagi, Chia-Ying Lee, Emilie Williams, Ross Carl
  • Publication number: 20140193974
    Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 10, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ying LEE, Jyu-Horng SHIEH
  • Publication number: 20140193980
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. Accordingly, first patterned second hard mask (HM) region is patterned, thus forming the line end space structure associated with an end-to-end space.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: Taiwan Semicondutor Manufacturing Compnay Limited
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20140193981
    Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: Taiwan Semiconductor Mnufacturing Company Limited
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
  • Publication number: 20140171343
    Abstract: A biological detecting chip comprising an optical fiber, at least one gas filter, an upper cap and a substrate is disclosed. The optical fiber has at least one detecting area disposed on an outer surface. The upper cap has at least two guiding channels passed through the upper cap, at least one discharge channel with two ends connecting to an upper portion of distinct guiding channels, an inlet and an outlet, wherein the gas filter is attached to an upside of the discharge channel to separate the discharge channel and an outside of the upper cap. The substrate has a test area and a plurality of directing channels, wherein the directing channel connects to the inlet and the guiding channel, connects to the guiding channel and the test area, and connects to the test area and the outlet.
    Type: Application
    Filed: January 18, 2013
    Publication date: June 19, 2014
    Applicant: ARDIC INSTRUMENTS CO.
    Inventors: YU CHENG SU, CHIA-YING LEE, CHIAO-TUNG CHANG, CHENG HAN CHEN
  • Publication number: 20140148005
    Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.
    Type: Application
    Filed: January 23, 2014
    Publication date: May 29, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying LEE, Jyu-Horng SHIEH
  • Publication number: 20140127897
    Abstract: A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects.
    Type: Application
    Filed: January 10, 2014
    Publication date: May 8, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying LEE, Jyu-Horng Shieh
  • Patent number: 8697537
    Abstract: A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh