Patents by Inventor ChiaHua Ho

ChiaHua Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861700
    Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Shi Jordan Lai, ChiaHua Ho, Fu-Liang Yang
  • Publication number: 20190051528
    Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 14, 2019
    Inventors: Fang-Shi Jordan Lai, ChiaHua Ho, Fu-Liang Yang
  • Patent number: 10103024
    Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Shi Jordan Lai, ChiaHua Ho, Fu-Liang Yang
  • Publication number: 20160181106
    Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Fang-Shi Jordan Lai, ChiaHua Ho, Fu-Liang Yang
  • Patent number: 9276209
    Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Shi Jordan Lai, ChiaHua Ho, Fu-Liang Yang
  • Patent number: 9076964
    Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: July 7, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang-Yeu Hsieh
  • Patent number: 9018615
    Abstract: A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Patent number: 8835894
    Abstract: The present invention discloses a resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 16, 2014
    Assignee: National Applied Research Laboratories
    Inventors: Ming-Daou Lee, ChiaHua Ho, Cho-Lun Hsu, Wen-Cheng Chiu
  • Patent number: 8697487
    Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: April 15, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai
  • Publication number: 20140073108
    Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.
    Type: Application
    Filed: November 14, 2013
    Publication date: March 13, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang-Yeu Hsieh
  • Patent number: 8597976
    Abstract: The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: December 3, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai
  • Patent number: 8587983
    Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: November 19, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20130260528
    Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.
    Type: Application
    Filed: May 17, 2013
    Publication date: October 3, 2013
    Applicant: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai
  • Publication number: 20130221313
    Abstract: The present invention discloses an ultra high density resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area.
    Type: Application
    Filed: April 20, 2012
    Publication date: August 29, 2013
    Inventors: Ming-Daou LEE, ChiaHua HO, Cho-Lun HSU, Wen-Cheng CHIU
  • Patent number: 8461564
    Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: June 11, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai
  • Patent number: 8243494
    Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: August 14, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh, Shih-Hung Chen
  • Patent number: 8178405
    Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: May 15, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Patent number: 8178388
    Abstract: Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: May 15, 2012
    Assignee: Macronix International Co., Ltd.
    Inventor: ChiaHua Ho
  • Patent number: 8158963
    Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: April 17, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang Yeu Hsieh
  • Patent number: 8139393
    Abstract: A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: March 20, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh