Patents by Inventor Chich-Neng Chang

Chich-Neng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200266095
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Publication number: 20200258771
    Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: April 26, 2020
    Publication date: August 13, 2020
    Inventors: Yu-Cheng Lin, Chich-Neng Chang, Bin-Siang Tsai
  • Patent number: 10692758
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 23, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Publication number: 20200185264
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Patent number: 10679893
    Abstract: An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 9, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Lin, Chich-Neng Chang, Bin-Siang Tsai
  • Publication number: 20200075395
    Abstract: An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventors: Yu-Cheng Lin, Chich-Neng Chang, Bin-Siang Tsai
  • Patent number: 10008409
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Publication number: 20180012793
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Patent number: 9812352
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is formed in the dielectric layer, in which the dielectric layer includes a damaged layer adjacent to the opening. Next, a dielectric protective layer is formed in the opening, a metal layer is formed in the opening, and the damaged layer and the dielectric protective layer are removed.
    Type: Grant
    Filed: January 31, 2016
    Date of Patent: November 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Publication number: 20170200632
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is formed in the dielectric layer, in which the dielectric layer includes a damaged layer adjacent to the opening. Next, a dielectric protective layer is formed in the opening, a metal layer is formed in the opening, and the damaged layer and the dielectric protective layer are removed.
    Type: Application
    Filed: January 31, 2016
    Publication date: July 13, 2017
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai