Patents by Inventor Chieh-Jen Ku

Chieh-Jen Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190326296
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Application
    Filed: April 18, 2018
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Publication number: 20190305081
    Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Travis W. LaJoie, Abhishek A. Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem O. Ogadhoh, Allen B. Gardiner, Blake C. Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
  • Publication number: 20190304897
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Travis LAJOIE, Abhishek SHARMA, Juan ALZATE-VINASCO, Chieh-Jen KU, Shem OGADHOH, Allen GARDINER, Blake LIN, Yih WANG, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI
  • Publication number: 20190237582
    Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.
    Type: Application
    Filed: August 18, 2017
    Publication date: August 1, 2019
    Inventors: Yicheng Lu, Wen-Chiang Hong, Chieh-Jen Ku, Kuang Sheng, Rui Li
  • Patent number: 9627439
    Abstract: A ZnO based display pixel structure that includes system-on-glass (SOG) substrates with embedded non-volatile resistive random access memory iNV-RRAM) is provided. Such pixels feature high frame rates and low power consumption. The entire SOG is based on ZnO devices. Different devices including TFT, TCO, RRAM, inverters, and shift registers are obtained through doping of different elements into selected ZnO active regions. This reduces the cost to package control circuitry onto a backplane of a display system, resulting in a low cost, light weight and uUra-thin display.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: April 18, 2017
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Chieh-Jen Ku
  • Patent number: 9590015
    Abstract: A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: March 7, 2017
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Yang Zhang, Chieh-Jen Ku
  • Publication number: 20150318332
    Abstract: A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.
    Type: Application
    Filed: November 10, 2014
    Publication date: November 5, 2015
    Inventors: Yicheng Lu, Yang Zhang, Chieh-Jen Ku
  • Patent number: 9064965
    Abstract: This application discloses ZnO film transistor-based immunosensors (ZnO-bioTFT), 2T biosensor arrays formed from two integrated ZnO-bioTFTs, 1T1R-based nonvolatile memory (NVM) arrays formed from ZnO-bioTFT (T) integrated with ZnO-based resistive switches (R), as well as integrated bioTFT (IBTFT) sensor systems formed from 2T biosensor arrays and 1T1R NVM arrays. Through biofunctionalization, these biosensors can perform immunosensing with high sensitivity and selectivity, and therefore have a wide range of applications, for example, in detecting target biomolecules or small molecules, and potential application in cancer diagnosis and treatment.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 23, 2015
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Pavel Ivanoff Reyes, Ki-Bum Lee, Aniruddh Solanki, Chieh-Jen Ku
  • Publication number: 20150155334
    Abstract: A ZnO based display pixel structure that includes system-on-glass (SOG) substrates with embedded non-volatile resistive random access memory iNV-RRAM) is provided. Such pixels feature high frame rates and low power consumption. The entire SOG is based on ZnO devices. Different devices including TFT, TCO, RRAM, inverters, and shift registers are obtained through doping of different elements into selected ZnO active regions. This reduces the cost to package control circuitry onto a backplane of a display system, resulting in a low cost, light weight and uUra-thin display.
    Type: Application
    Filed: May 8, 2013
    Publication date: June 4, 2015
    Applicant: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Chieh-Jen Ku
  • Patent number: 8884285
    Abstract: A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 11, 2014
    Assignee: Rutgers, The State University of New Jersey
    Inventors: Yicheng Lu, Yang Zhang, Chieh-Jen Ku
  • Publication number: 20140027702
    Abstract: A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.
    Type: Application
    Filed: March 1, 2013
    Publication date: January 30, 2014
    Applicant: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Yang Zhang, Chieh-Jen Ku