Patents by Inventor Chieh-Te Chen

Chieh-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150228734
    Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
    Type: Application
    Filed: April 27, 2015
    Publication date: August 13, 2015
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Publication number: 20150214068
    Abstract: A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen
  • Patent number: 9054172
    Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 9, 2015
    Assignee: UNITED MICROELECTRNICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Publication number: 20150126015
    Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.
    Type: Application
    Filed: December 25, 2014
    Publication date: May 7, 2015
    Inventors: Chieh-Te Chen, Yi-Po Lin, Jiunn-Hsiung Liao, Shui-Yen Lu, Li-Chiang Chen
  • Patent number: 9023708
    Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Li-Chiang Chen, Jiunn-Hsiung Liao, Hsuan-Hsu Chen, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai, Ching-Pin Hsu
  • Patent number: 8993433
    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung
  • Patent number: 8962490
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang, Chieh-Te Chen
  • Patent number: 8952392
    Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yi-Po Lin, Jiunn-Hsiung Liao, Shui-Yen Lu, Li-Chiang Chen
  • Patent number: 8916475
    Abstract: A patterning method is provided. A mask composite layer and a first tri-layer photoresist are sequentially formed on a target layer. A first etching is performed to the mask composite layer, using the first tri-layer photoresist as a mask, to form at least one first opening in an upper portion of the mask composite layer. The first tri-layer photoresist is removed. A second tri-layer photoresist is formed on the mask composite layer. A second etching is performed to the mask composite layer, using the second tri-layer photoresist as a mask, to form at least one second opening in the upper portion of the mask composite layer. The second tri-layer photoresist is removed. A lower portion of the mask composite layer is patterned by using the upper portion of the mask composite layer as a mask. The target layer is patterned by using the patterned mask composite layer as a mask.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: December 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen, Cheng-Hsing Chuang
  • Publication number: 20140349236
    Abstract: A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang
  • Publication number: 20140349476
    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
    Type: Application
    Filed: May 27, 2013
    Publication date: November 27, 2014
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung
  • Publication number: 20140346575
    Abstract: A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench.
    Type: Application
    Filed: May 27, 2013
    Publication date: November 27, 2014
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen
  • Publication number: 20140342553
    Abstract: According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen, Yu-Tsung Lai, Chih-Sen Huang, Ching-Wen Hung
  • Publication number: 20140315365
    Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Li-Chiang Chen, Jiunn-Hsiung Liao, Hsuan-Hsu Chen, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai, Ching-Pin Hsu
  • Patent number: 8835324
    Abstract: In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yi-Po Lin, Feng-Yih Chang, Chih-Wen Feng, Shang-Yuan Tsai
  • Publication number: 20140241027
    Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Po-Chao Tsao, Shu-Ru Wang, Chia-Wei Huang, Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang
  • Patent number: 8785283
    Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 22, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
  • Publication number: 20140151763
    Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Publication number: 20140154852
    Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
  • Patent number: 8728949
    Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 20, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Ling Shih, Shin-Chi Chen, Chieh-Te Chen, Wei-Hang Huang