Abstract: A physiological sensing device for sensing physiological signal of an organism is provided. The physiological sensing device includes a sensing chip, a coupling sensing electrode and a coupling dielectric stacked layer. The coupling sensing electrode is electrically connected to the sensing chip. The coupling dielectric stacked layer covers the coupling sensing electrode. The coupling dielectric stacked layer is located between the coupling sensing electrode and the organism. The coupling dielectric stacked layer includes a first dielectric layer and a second dielectric layer. The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer. The second dielectric layer is located between the first dielectric layer and the organism.

Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.

Abstract: A stacked wiring structure includes a first wiring substrate and a second wiring substrate. The first wiring substrate includes a first glass substrate, multiple first conductive through vias penetrating through the first glass substrate, and a first multi-layered redistribution wiring structure disposed on the first glass substrate. The second wiring substrate includes a second glass substrate, multiple second conductive through vias penetrating through the second glass substrate, and a second multi-layered redistribution wiring structure disposed on the second glass substrate. The first conductive through vias are electrically connected to the second conductive through vias. The first glass substrate is spaced apart from the second glass substrate. The first multi-layered redistribution wiring structure is spaced apart from the second multi-layered redistribution wiring structure by the first glass substrate and the second glass substrate.

Abstract: An electronic device including a pixel array structure, a redistribution structure, and a plurality of conductive via structures is provided. The pixel array structure includes a plurality of signal lines. The redistribution structure overlaps the pixel array structure and includes a plurality of conductive lines. The conductive via structures electrically connect the signal lines of the pixel array structure and the conductive lines of the redistribution structure. At least one of the conductive via structures shares at least one conductive layer with the pixel array structure.

Abstract: Provided a filter and a redistribution layer structure including the same. The capacitor includes a first electrode, a second electrode, a third electrode, a dielectric layer, and a conductive through via. The second electrode is disposed above the first electrode. The third electrode is disposed between the first electrode and the second electrode. The dielectric layer is disposed between the first electrode and the third electrode and between the second electrode and the third electrode. The conductive through via penetrates the dielectric layer and the third electrode to be connected to the first electrode and the second electrode, and is electrically separated from the third electrode. The first electrode and the second electrode are signal electrodes, and the third electrode is a ground electrode.

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

Abstract: A pixel structure is provided. The pixel structure includes a substrate and a conductive line electrically connected to the substrate. The ratio of the height to the width of the conductive line is between 0.5 and 6. The pixel structure also includes an electrode electrically connected to the conductive line and a conversion element electrically connected to the conductive lines through the electrode.

Abstract: The present disclosure provides a package structure, an antenna module, and a probe card. The package structure includes a connection member and a first redistribution structure disposed on the connection member. The connection member includes a conductive connector and an insulation layer surrounding the conductive connector. The first redistribution structure includes a first dielectric layer, and a first wiring pattern, and a first device. The first dielectric layer is disposed on the connection member. The first wiring pattern is disposed in the first dielectric layer. The first device is disposed above the first dielectric layer and is electrically connected to the conductive connector.

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

Abstract: Provided are a capacitor and a filter and a redistribution layer structure including the same. The capacitor includes a first electrode, a second electrode, a third electrode, a dielectric layer, and a conductive through via. The second electrode is disposed above the first electrode. The third electrode is disposed between the first electrode and the second electrode. The dielectric layer is disposed between the first electrode and the third electrode and between the second electrode and the third electrode. The conductive through via penetrates the dielectric layer and the third electrode to be connected to the first electrode and the second electrode, and is electrically separated from the third electrode. The first electrode and the second electrode are signal electrodes, and the third electrode is a ground electrode.

Abstract: A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1?(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.

Abstract: An electronic device including a pixel array structure, a redistribution structure, and a plurality of conductive via structures is provided. The pixel array structure includes a plurality of signal lines. The redistribution structure overlaps the pixel array structure and includes a plurality of conductive lines. The conductive via structures electrically connect the signal lines of the pixel array structure and the conductive lines of the redistribution structure. At least one of the conductive via structures shares at least one conductive layer with the pixel array structure.

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.

Abstract: A swimming posture correction method and a swimming posture correction system, adapted for a computing apparatus to correct a swimming posture of a swimmer using at least two gravity sensors, are provided. The gravity sensors are respectively disposed at ends of at least two limbs of the swimmer performing a relative stroke action. In the method, body parameters of the swimmer are obtained and a reference index of coordination for implementing a swimming posture suitable for the body parameters is captured. A stroke of the limb is monitored using the gravity sensors to obtain a timing diagram of the limbs performing a stroke promotion action. Then, an index of coordination of the swimmer is calculated by analyzing the timing diagram and compared with the reference index of coordination so as to prompt for correcting the swimming posture according to a comparison result.

Abstract: A swimming posture correction method and a swimming posture correction system, adapted for a computing apparatus to correct a swimming posture of a swimmer using at least two gravity sensors, are provided. The gravity sensors are respectively disposed at ends of at least two limbs of the swimmer performing a relative stroke action. In the method, body parameters of the swimmer are obtained and a reference index of coordination for implementing a swimming posture suitable for the body parameters is captured. A stroke of the limb is monitored using the gravity sensors to obtain a timing diagram of the limbs performing a stroke promotion action. Then, an index of coordination of the swimmer is calculated by analyzing the timing diagram and compared with the reference index of coordination so as to prompt for correcting the swimming posture according to a comparison result.

Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.

Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.