Patents by Inventor Chieh-Yen Chen
Chieh-Yen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929333Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.Type: GrantFiled: May 10, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
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Publication number: 20240079392Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang WANG, Tso-Jung Chang, Jeng-Shien Hsieh, Shih-Ping Lin, Chih-Peng Lin, Chieh-Yen Chen, Chen-Hua Yu
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Publication number: 20240047365Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure and a second chip structure over a carrier substrate. The method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. The interconnection structure has multiple dielectric layers and multiple conductive features. One of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. The method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.Type: ApplicationFiled: January 5, 2023Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Jeng-Shien HSIEH, Shih-Ping LIN, Chieh-Yen CHEN, Chen-Hua YU
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Publication number: 20240038669Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.Type: ApplicationFiled: July 20, 2023Publication date: February 1, 2024Inventors: Chen-Hua Yu, Chieh-Yen Chen, Chuei-Tang Wang, Chung-Hao Tsai
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Publication number: 20230420437Abstract: A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Inventors: Chieh-Yen Chen, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
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Publication number: 20230378080Abstract: A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Chen-Hua Yu, Jeng-Shien Hsieh, Chuei-Tang Wang, Chieh-Yen Chen
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Publication number: 20230369302Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.Type: ApplicationFiled: July 21, 2023Publication date: November 16, 2023Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang, Chieh-Yen Chen
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Patent number: 11784172Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.Type: GrantFiled: April 16, 2021Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING HSINCHU, CO., LTD.Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang, Chieh-Yen Chen
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Patent number: 11769731Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.Type: GrantFiled: April 13, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chen-Hua Yu, Chieh-Yen Chen, Chuei-Tang Wang, Chung-Hao Tsai
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Publication number: 20230260872Abstract: A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.Type: ApplicationFiled: February 16, 2022Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Shiang Liao, Chieh-Yen Chen, Chuei-Tang Wang
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Publication number: 20230253351Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.Type: ApplicationFiled: January 7, 2022Publication date: August 10, 2023Inventors: Chuei-Tang Wang, Wei Ling Chang, Chieh-Yen Chen, Chen-Hua Yu
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Patent number: 11621244Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.Type: GrantFiled: November 15, 2019Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Chuei-Tang Wang, Chieh-Yen Chen, Wei Ling Chang
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Patent number: 11600431Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.Type: GrantFiled: November 9, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chuei-Tang Wang, Wei-Ting Chen, Chieh-Yen Chen, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo, Chen-Hua Yu
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Patent number: 11532533Abstract: In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.Type: GrantFiled: May 22, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Fong-yuan Chang, Chieh-Yen Chen
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Patent number: 11527486Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.Type: GrantFiled: December 14, 2020Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
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Publication number: 20220359333Abstract: In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Fong-Yuan Chang, Chieh-Yen Chen
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Publication number: 20220359467Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Chen-Hua Yu, Chuei-Tang Wang, Chieh-Yen Chen, Wei Ling Chang
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Publication number: 20220352082Abstract: A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Inventors: Chen-Hua Yu, Jeng-Shien Hsieh, Chuei-Tang Wang, Chieh-Yen Chen
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Publication number: 20220336431Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
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Publication number: 20220270990Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu