Abstract: An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.

Abstract: An electronic device includes a sense amplifier. The sense amplifier includes a pair of load transistors cross-coupled to each other, a pair of input transistors coupled to the pair of load transistors, a first current path, and a second current path. The pair of input transistors is configured to receive a pair of input signals and enable generation of a pair of output signals from the pair of input signals during a duty cycle of a clock signal. The first current path is coupled to the pair of input transistors via a tail node and controlled by the clock signal to couple the tail node to a power supply and enable generation of the pair of output signals during the duty cycle of the clock signal. A second current path electrically couples the tail node to the power supply, independently of switching of the clock signal.

Abstract: An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.

Abstract: An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits.

Abstract: Method and apparatus for a display bridge with support for multiple display interfaces are disclosed. The novel display bridge comprises a predriver configured to provide data input signals. A shared output driver is configured to receive the data input signals and provide output display signals compatible for driving MIPI-DSI, EDP, or LVDS displays. A regulator and current source is coupled to the shared output driver configured to regulate the shared output driver operating voltage and provide a current source for the shared output driver. A shared termination output coupled to the shared output driver is configured to provide termination resistance for the output display signals and termination voltage for the termination resistance.

Abstract: A switched capacitor digital-to-analog converter (“DAC”) for converting a digital input code to an analog signal comprises a switched capacitor array and a reset switch having a first end and a second end. The digital input code is inputted to the switched capacitor array. The switched capacitor array is connected to a summation node. The first end of the reset switch is connected to the summation node and the second end of the reset switch is connected to a common mode voltage. The reset switch is closed after a plurality of sampling cycles. The analog signal is provided based on a summation voltage at the summation node.

Abstract: A modem for communicating application data over a voice channel comprises an adaptive modulator, a mixer, and a vocoder. The adaptive modulator modulates application data as a function of a source application of the application data and feedback information of the voice channel. The modulated data is inputted to the mixer. The vocoder processes the mixed data for transmission through the voice channel.

Abstract: A dynamic element matching method for a multi-unit-element digital-to-analog converter having unit elements comprises several steps. An element selection probability is determined as a function of a number of the unit elements and a digital signal. Next, loop filter output signals are generated as a function of the determined element selection probability and control signals for the unit elements. Certain ones of the unit elements are selected as a function of the generated loop filter output signals. The selected certain ones of the unit elements are activated for output of the converter.

Abstract: A transmitter, comprises: a first branch for providing a positive output having a first set of serially-connected transistors; a second branch for providing a negative output having a second set of serially-connected transistors; and a biasing circuit, wherein the biasing circuit generates a first biasing voltage and a second biasing voltage as a function of the positive output, the negative output, and a predefined threshold voltage, and wherein the first biasing voltage, the second biasing voltage, and a differential input signal drive the first set of serially-connected transistors and the second set of serially-connected transistors.

Abstract: A dynamic element matching method for a multi-unit-element digital-to-analog converter having unit elements comprises several steps. An element selection probability is determined as a function of a number of the unit elements and a digital signal. Next, loop filter output signals are generated as a function of the determined element selection probability and control signals for the unit elements. Certain ones of the unit elements are selected as a function of the generated loop filter output signals. The selected certain ones of the unit elements are activated for output of the converter.

Abstract: A modem for communicating application data over a voice channel comprises an adaptive modulator, a mixer, and a vocoder. The adaptive modulator modulates application data as a function of a source application of the application data and feedback information of the voice channel. The modulated data is inputted to the mixer. The vocoder processes the mixed data for transmission through the voice channel.

Abstract: A transmitter, comprises: a first branch for providing a positive output having a first set of serially-connected transistors; a second branch for providing a negative output having a second set of serially-connected transistors; and a biasing circuit, wherein the biasing circuit generates a first biasing voltage and a second biasing voltage as a function of the positive output, the negative output, and a predefined threshold voltage, and wherein the first biasing voltage, the second biasing voltage, and a differential input signal drive the first set of serially-connected transistors and the second set of serially-connected transistors.

Abstract: Method and apparatus for a display bridge with support for multiple display interfaces are disclosed. The novel display bridge comprises a predriver configured to provide data input signals. A shared output driver is configured to receive the data input signals and provide output display signals compatible for driving MIPI-DSI, EDP, or LVDS displays. A regulator and current source is coupled to the shared output driver configured to regulate the shared output driver operating voltage and provide a current source for the shared output driver. A shared termination output coupled to the shared output driver is configured to provide termination resistance for the output display signals and termination voltage for the termination resistance.

Abstract: Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.

Abstract: An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Abstract: An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

Abstract: A transceiving system utilizing a shared filter module is provided. The shared filter module is selectively filtering signals in a first band in a first mode and a second band in a second mode. The first mode is a receiver mode whereas the second mode is a transmission mode. The shared filter module comprises a compound filter comprising two low pass filters and a coupling controller to manage input and output wiring of the low pass filters. When the coupling controller is enabled in the first mode, the compound filter acts as a bandpass filter. When the coupling controller is disabled, the compound filter acts as two independent low pass filters.

Abstract: A display apparatus including a process module, a screen and an electric module is provided. The process module determines the display mode of an image according to the format of the image. The screen coupling the process module displays the image. The electric module coupling the screen and the process module adjusts the screen in the orientation in accordance with the display mode of the image. Thus, the display apparatus automatically adjusts the screen in the orientation in accordance with whether the display mode of an image is in the portrait mode or the landscape mode.

Abstract: A spread spectrum receiver whose de-spreading process based on transformed spreading codes is provided. Instead of de-spreading with original spreading codes, this approach de-spreads received signal with the spreading codes transformed from the original codes in order to eliminate the negative impact of system impairments such as frequency offset to a spread spectrum receiver. Before de-spreading with the transformed code, the received signal goes through the same transformation as the original codes do. After a transformation, the transformed codes may exist some undesirable property such as spreading code having DC content. An approach is given to cancel unwanted side effects relating the transformed spreading codes. The approaches are very effective for spread spectrum system based on frequency modulation scheme such as MSK.