Patents by Inventor Chien-Chih Lee
Chien-Chih Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240111337Abstract: An electronic device including a body and a receptacle connector is provided. The body has a side wall surface, a receptacle slot located at the side wall surface, a waterproof protrusion protruding from the side wall surface, and two gutters located at the side wall surface, where the waterproof protrusion is located above the receptacle slot, and the two gutters are respectively located at two opposite sides of the receptacle slot. The receptacle connector is disposed in the receptacle slot.Type: ApplicationFiled: May 8, 2023Publication date: April 4, 2024Applicant: Acer IncorporatedInventors: Wei-Chih Wang, Chen-Min Hsiu, Chien-Yu Lee, Szu-Wei Yang, Fang-Ying Huang
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Publication number: 20240102860Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.Type: ApplicationFiled: September 5, 2023Publication date: March 28, 2024Inventors: Cheng Chih HSIEH, Tien Chi WU, Ming-Long LEE, Yu-Hsuan LIN, Tsung-I LIN, Chien-Hao MA
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Publication number: 20240107731Abstract: The present disclosure provides a matte-type electromagnetic interference shielding film including bio-based components, which includes a bio-based insulating layer, a bio-based adhesive layer, a metal layer, and a bio-based electrically conductive adhesive layer. The matte-type electromagnetic interference shielding film including the bio-based component of the present disclosure has a matte appearance and high bio-based content and has the advantages of good surface insulation, high surface hardness, good chemical resistance, high shielding performance, good adhesion strength, low transmission loss, high transmission quality, good operability, high heat resistance, and the inner electrically conductive adhesive layer with long shelf life and storage life. The present disclosure further provides a preparation method thereof.Type: ApplicationFiled: July 14, 2023Publication date: March 28, 2024Inventors: Bo-Sian DU, Wei-Chih LEE, Chia-Hua HO, Chih-Ming LIN, Chien-Hui LEE
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Publication number: 20240101602Abstract: Provided is a peptide and method in preventing or treating infections caused by a wide spectrum of pathogens, including bacteria and fungus in hosts such as plants and animals. Methods of preventing or treating plant diseases and infection in animals are also provided.Type: ApplicationFiled: November 24, 2021Publication date: March 28, 2024Inventors: Rita P.Y. Chen, Chiu-Ping CHENG, Chien-Chih YANG, Kung-Ta LEE, Ying-Lien CHEN, Li-Hang Hsu, Hsin-Liang CHEN, Sung CHEN
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Patent number: 11936238Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.Type: GrantFiled: June 15, 2022Date of Patent: March 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Hsin-Chih Chen, Hung-Chieh Lin, Chao-Lung Kuo, Yi-Ping Hsieh, Chien-Shien Lee
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Patent number: 11930573Abstract: A power supply device is provided. The power supply device includes a power converter and a controller. The controller controls the power converter to generate an output power. The controller includes a first detection circuit and a second detection circuit. The first detection circuit detects the output power to obtain a first detection result. The first detection result is a variation of an output current value of the output power. The second detection circuit detects electrical characteristics other than the output current value to obtain a second detection result. The controller determines whether to limit output of the output power according to a relationship between the first detection result and the second detection result.Type: GrantFiled: October 5, 2022Date of Patent: March 12, 2024Assignee: Power Forest Technology CorporationInventors: Rong-Jie Tu, Hung-Chih Chiu, Chien-Lung Lee
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Publication number: 20230326802Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.Type: ApplicationFiled: June 5, 2023Publication date: October 12, 2023Inventors: Szu-Chi Yang, Allen Chien, Tsai-Yu Huang, Chien-Chih Lin, Po-Kai Hsiao, Shih-Hao Lin, Chien-Chih Lee, Chih Chieh Yeh, Cheng-Ting Ding, Tsung-Hung Lee
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Patent number: 11670551Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.Type: GrantFiled: July 10, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
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Patent number: 11081774Abstract: A negative coupling structure applied in a dielectric waveguide filter includes an elongated blind hole formed on a first surface of a dielectric body for building the negative coupling structure, and tuning holes formed on the first surface or a second surface of the dielectric body. A first coupling portion configured to be corresponsive to a bottom wall of the elongated blind hole, a second coupling portion configured to be corresponsive to a side wall of the elongated blind hole, and a common coupling portion connected between the bottom wall and the side wall are provided to define a negative coupling structure in the dielectric body, so as to provide both capacitive coupling and inductive coupling and a negative coupling and achieve the effects of reducing the weight and volume of the dielectric waveguide filter and providing good performance, simple structure and easy manufacture.Type: GrantFiled: March 25, 2020Date of Patent: August 3, 2021Inventors: Chien-Chih Lee, Yu-Fu Chen, Hsueh-Han Chen
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Publication number: 20210098305Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.Type: ApplicationFiled: July 10, 2020Publication date: April 1, 2021Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
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Patent number: 10951191Abstract: Provided is a low-leakage automatic adjustable diplexer including a body, a thin plate and two resonant regulators. The body has therein cuboid waveguide channels each having a feeding portion, a reception port portion, a transmission port portion, a fitting portion, a first filtering portion, a second filtering portion, first E/H conversion units connected to two ends of the first filtering portion, respectively, and second E/H conversion units connected to two ends of the second filtering portion, respectively. The thin plate is clamped inside the body. The resonant regulators each have a plurality of frequency disturbance elements adjustably protruding into the first and second filtering portions.Type: GrantFiled: December 25, 2019Date of Patent: March 16, 2021Inventors: Jen-Ti Peng, Chien-Chih Lee, Cheng-Lung Wu, Meng-Hung Hsieh, You-Hua Wu
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Patent number: 10790795Abstract: A zeroing structure applicable to an adjustable diplexer includes a substrate, holder, motor, lead screw, displacement plate, stop element and interference element. The holder is disposed on the substrate. The motor is disposed on the holder. The lead screw is rotatably disposed on the holder and connected to the motor, and thus rotation of the lead screw is driven by the motor. The displacement plate is movably disposed on the substrate and helically connected to the lead screw so as to undergo linear motion between a first position and a second position relative to the substrate when guided and driven by the motor. The stop element is disposed on the lead screw. The interference element is disposed on the displacement plate and at the position that allows the interference element to come into contact with the stop element when the displacement plate is at the first position.Type: GrantFiled: December 25, 2019Date of Patent: September 29, 2020Inventors: Jen-Ti Peng, Chien-Chih Lee, Cheng-Lung Wu, Tsung-Hsien Tsai, Chia-Hao Hsu, Chih-Sheng Tsai
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Patent number: 10498054Abstract: A jumper is adapted to be disposed between two sockets. Each of the sockets has at least one conductive terminal. The jumper includes an insulative body and at least one conductive body, which includes a main body portion, a first engaging portion, and a second engaging portion. The main body portion is connected to the insulative body. The first and second engaging portions are respectively located at two opposite sides of the main body portion, and extend respectively from two opposite sides of the insulative body. The first engaging portion engages the conductive terminal of one of the sockets. The second engaging portion engages the conductive terminal of another one of the sockets, such that the conductive terminals are electrically connected. A power distribution device is also provided.Type: GrantFiled: October 29, 2018Date of Patent: December 3, 2019Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology CorporationInventors: Shih-Ming Chen, Chien-Chih Lee, Yong-Long Lee, Kun-Ta Yang
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Patent number: 9620500Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: GrantFiled: May 18, 2016Date of Patent: April 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh
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Patent number: 9568008Abstract: A rotor structure of a fan includes a bushing, a hub, a shaft and a plurality of blades. The hub has a top portion and a sidewall, and the top portion of the hub covers the bushing. The hub and the bushing are made by the same material. One end of the shaft is connected to the bushing, and the shaft is disposed inside the top portion. The blades are disposed on the outer side of the sidewall of the hub. A manufacturing method of the rotor structure is also disclosed.Type: GrantFiled: December 30, 2013Date of Patent: February 14, 2017Assignee: DELTA ELECTRONICS, INC.Inventors: Yueh-Lung Huang, Chien-Ming Lee, Tine-Kun Lin, Hai-Feng Li, Ming-Kai Hsieh, Chien-Chih Lee
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Patent number: 9515387Abstract: A MIMO (Multi-Input Multi-Output) antenna includes a system ground plane, an antenna ground plane, an EBG (Electromagnetic Band-Gap) structure, a first antenna element, and a second antenna element. The antenna ground plane overlaps a first portion of the system ground plane. The EBG structure is formed on a second portion of the system ground plane. The first antenna element and the second antenna element are both disposed in proximity to the EBG structure, but substantially extend in different directions.Type: GrantFiled: August 17, 2012Date of Patent: December 6, 2016Assignee: MEDIATEK INC.Inventors: Kuo-Fong Hung, Ho-Chung Chen, Mao-Lin Wu, Chien-Chih Lee
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Publication number: 20160260713Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: ApplicationFiled: May 18, 2016Publication date: September 8, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi WANG, Chien-Chih LEE, Tien-Wei CHIANG, Ching-Wei TSAI, Chih-Ching WANG, Jon-Hsu HO, Wen-Hsing HSIEH
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Patent number: 9373620Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: GrantFiled: September 12, 2014Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh
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Publication number: 20160079239Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Chin-Chi WANG, Chien-Chih LEE, Tien-Wei CHIANG, Ching-Wei TSAI, Chih-Ching WANG, Jon-Hsu HO, Wen-Hsing HSIEH