Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract: A circuit board mounting apparatus includes a circuit board, a first mounting member, a second mounting member, and a third mounting member. The first and second mounting members are mounted to a front side of the circuit board. The third mounting member is mounted to a rear side of the circuit board. The circuit board is capable of being mounted to a first side plate of a first chassis in a perpendicular manner by the first and second mounting members, or is capable of being mounted to a second side plate of a second chassis in a parallel manner by the first, second, and third mounting members.

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract: A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer.

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract: An LED base module includes a substrate and several driving units disposed on the substrate. Each driving unit includes a circuit layer, a separating wall, an LED driving component, a packaging member, and two electrodes. The circuit layer, the separating wall, and the electrodes are disposed on the substrate. A portion of the substrate corresponding to each driving unit is provided with an LED area and an electronic component area defined by the separating wall. The LED driving component is disposed on a portion of the circuit layer arranged in the electronic component area. The packaging member is formed on the electronic component area to entirely cover the LED driving component. A portion of the circuit layer arranged in the LED bonding area is used to bond to an LED chip, and the separating wall is configured to separate the LED chip and the LED driving component.

Abstract: A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data. A terminal of first capacitor couples to another source/drain of first transistor. A gate and a source/drain of second transistor couple to another terminal of first capacitor; and another source/drain thereof receives a switch signal. A terminal of second capacitor receives a reset signal; and another terminal thereof couples to another terminal of first capacitor. A gate of third transistor couples to a terminal of first capacitor. A gate of fourth transistor receives an enable signal; a source/drain thereof couples to a first power supply voltage; and another source/drain thereof couples to one source/drain of third transistor. The anode and cathode of the light emitting element couple to one source/drain of third transistor and a second power supply voltage, respectively.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.

Abstract: A dual screen electronic device includes a main device having a first casing and a display screen, and a detachable display module. The first casing has a first opening. The display screen is located on the first casing and exposed from the first opening. The detachable display module includes a second casing, a power supply module, an electrophoretic display (EPD) module, and a control module. The second casing is detachably positioned on the first casing, and has a second opening. The power supply module is arranged on the second casing. The EPD module is fixed to the second casing, or is detachably positioned on the second casing, and has a display region exposed from the second opening. The control module is selectively located on the second casing or on the EPD module, and is electrically connected to the EPD module and the power supply module.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract: A method of manufacturing a LED package structure for preventing lateral light leakage includes placing a plurality of light-emitting units on a carrier substrate, the light-emitting units being electrically connected to the carrier substrate; forming a plurality of light-transmitting gel bodies on the carrier substrate for respectively enclosing the light-emitting units, the light-transmitting gel bodies being separated from each other to form a gel receiving space among the light-transmitting gel bodies; forming a light-shielding gel body to fill up the gel receiving space; and then cutting the carrier substrate and the light-shielding gel body to form the plurality of LED package structures separated from each other, the carrier substrate being cut to form a plurality of circuit substrates for respectively carrying the light-emitting units.

Abstract: The present disclosure provides a bottom electrode substrate for a segment-type electrophoretic display. The bottom electrode substrate includes a flexible substrate, a first conductive layer, an insulating layer, a second conductive layer and a segment-type electrode. The first conductive layer is disposed on the flexible substrate. The insulating layer covers the first conductive layer and the flexible substrate, wherein the insulating layer has at least one opening exposing a part of the first conductive layer. The second conductive layer is filled in the opening and in contact with the exposed first conductive layer. The segment-type electrode covers the second conductive layer and the insulating layer, and is in contact with the second conductive layer. A method for manufacturing the bottom electrode substrate is also provided herein.

Abstract: An LED package structure for preventing lateral light leakage includes a substrate unit, a light-emitting unit, a light-transmitting unit and a light-shielding unit. The substrate unit includes a circuit substrate. The light-emitting unit includes at least one LED chip disposed on the circuit substrate and electrically connected to the circuit substrate. The light-transmitting unit includes a light-transmitting gel body disposed on the circuit substrate for enclosing the LED chip. The light-transmitting gel body has a first light-transmitting portion disposed on the circuit substrate for enclosing the LED chip and at least one second light-transmitting portion projected upwardly from the first light-transmitting portion and corresponding to the LED chip, and the second light-transmitting portion has a light output surface. The light-shielding unit includes a light-shielding gel body disposed on the circuit substrate for exposing the light output surface of the second light-transmitting portion.

Abstract: A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data. A terminal of first capacitor couples to another source/drain of first transistor. A gate and a source/drain of second transistor couple to another terminal of first capacitor; and another source/drain thereof receives a switch signal. A terminal of second capacitor receives a reset signal; and another terminal thereof couples to another terminal of first capacitor. A gate of third transistor couples to a terminal of first capacitor. A gate of fourth transistor receives an enable signal; a source/drain thereof couples to a first power supply voltage; and another source/drain thereof couples to one source/drain of third transistor. The anode and cathode of the light emitting element couple to one source/drain of third transistor and a second power supply voltage, respectively.

Abstract: A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer.

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract: A mobile display system includes a first mobile display device and a second mobile display device. The first mobile display device includes a first power storage module, a first screen, and a wireless power transmitter. The first screen is configured to display a first image by using the power stored in the first power storage module. The second mobile display device includes a second power storage module, a second screen, and a wireless power receiver. The second screen is configured to display a second image by using the power stored in the second power storage module. During a period when the first power storage module is charged, the wireless power transmitter provides a first wireless power signal to the wireless power receiver, so as to charge the second power storage module by the first wireless power signal.

Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.