Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth.

Abstract: The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.

Abstract: A yellow phosphor having oxyapatite structure, preparation method and white light-emitting diode thereof are disclosed. The yellow phosphor has a chemical formula of (A1?xEux)8?yB2+y(PO4)6?y(SiO4)y(O1?zSz)2, wherein A and Eu are divalent metal ions, B is a trivalent metal ion, 0<x?0.6, 0?y?6, and 0?z?1. A can be an alkaline earth metal, Mn or Zn. B can be a group 13 metal, a rare earth meal or Bi.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: A article includes a substrate and a metal dielectric reflective film. The metal dielectric reflective film is formed on the substrate, the metal dielectric reflective film includes a dielectric multiple layer and a metal layer. The dielectric multiple layer includes a first layer, a second layer, a third layer, and a fourth layer arranged in the order written and stacked one on another. The first and third layers comprised of a low refractive index material, the second and fourth layers comprised of a high refractive index material. The metal layer is disposed on the fourth layer.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: An exemplary wet coating system includes a coating chamber, an annealing chamber, an unloading chamber, and a mechanical arm. The coating chamber is configured for allowing a substrate being wet coated therein. The unloading chamber is configured for allowing the substrate being unloaded therein. The annealing chamber is interposed between and communicated with the coating chamber and the unloading chamber and is configured for allowing the substrate being annealed therein. The communicated coating chamber, annealing chamber, and unloading chamber are vacuumized. The mechanical arm is configured for holding the substrate and moving the substrate across the coating chamber, the annealing chamber, and the unloading chamber.

Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

Abstract: A multilayer substrate includes a base layer, a coating layer and an intermediate layer positioned between the base layer and the coating layer. The intermediate layer contains chromium and nitrogen. A content of the chromium in the intermediate layer gradually decreases from the base layer to the coating layer.

Abstract: A yellow phosphor having oxyapatite structure, preparation method and white light-emitting diode thereof are disclosed. The yellow phosphor has a chemical formula of (A1?xEux)8?yB2+y(PO4)6?y(SiO4)y(O1?zSz)2, wherein A and Eu are divalent metal ions, B is a trivalent metal ion, 0<x?0.6, 0?y?6, and 0?z?1. A can be an alkaline earth metal, Mn or Zn. B can be a group 13 metal, a rare earth meal or Bi.

Abstract: A carrier for transmitting a high frequency signal and a carrier layout method thereof are provided. The carrier includes a substrate, conducting wires and reference planes both formed on the substrate. The carrier layout method includes defining impedance and thickness of the carrier according to the high frequency signal and defining layout parameters according to the impedance and the thickness. The layout parameters include a conducting layer formed on the conducting wires, a coplanar waveguide encompasses both the reference planes and the conducting wires as a part thereof, roughness portions formed on the conducting wires, recessed portions formed on the conducting wires, and the substrate being a high loss tangent substrate. The layout is performed according to the layout parameters defined thereabove, so as to increase loss of the high frequency signal in transmission.

Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

Abstract: A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 81.76 to about 83.76, a value of a* in a range from about ?0.63 to about 0.37 and a value of b* in a range from about ?1.04 to about ?0.04 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided.