Abstract: Some embodiments relate to a memory device. The memory device includes a substrate comprising an inter-metal dielectric layer having a metal line, a dielectric layer over the substrate, a bottom electrode via through the dielectric layer and in contact with the metal line, a bottom electrode over the bottom electrode via, a magnetic tunneling junction (MTJ) element over the bottom electrode, and a top electrode over the MTJ element. A center portion of the bottom electrode directly above the bottom electrode via is thicker than an edge portion of the bottom electrode.

Abstract: Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

Abstract: An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.

Abstract: An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a metal pattern, and forming an etch stop layer over the substrate. The etch stop layer includes a first material. The method also includes forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer, and forming an insulative layer over the etch stop layer. The diffused area includes a lower etch rate to a first etchant than the insulative layer. A semiconductor device is also provided.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a metal pattern, and forming an etch stop layer over the substrate. The etch stop layer includes a first material. The method also includes forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer, and forming an insulative layer over the etch stop layer. The diffused area includes a lower etch rate to a first etchant than the insulative layer. A semiconductor device is also provided.