Patents by Inventor Chien-Hua Huang

Chien-Hua Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10068770
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Publication number: 20180240790
    Abstract: A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 23, 2018
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 10032640
    Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Ming-Hui Weng, Tzu-Hui Wei
  • Patent number: 10002820
    Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Rong Jan, Che-Yu Yeh, Chee Wee Liu, Chien-Hua Huang, Bing J. Sheu
  • Patent number: 9947646
    Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Publication number: 20180096850
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 9934987
    Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee
  • Publication number: 20180076132
    Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 15, 2018
    Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
  • Patent number: 9831090
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 9818690
    Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
  • Patent number: 9735048
    Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
  • Publication number: 20170229440
    Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 10, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9685138
    Abstract: A brightness controlling method for an all-in-one computer is provided. The all-in-one computer includes an on-screen display adjusting unit having a first brightness value, an operating system having a first system brightness value, a control unit and a scaler. The brightness controlling method includes the following steps. First, the first brightness value is adjusted to a second brightness value or the first system brightness value is adjusted to a second system brightness value. Then, when the first brightness value is adjusted to the second brightness value, the control unit synchronizes the first system brightness value to the second brightness value; when the first system brightness value is adjusted to the second system brightness value, the scaler adjusts the first brightness value to the second system brightness value. The invention also provides an all-in-one computer implementing the brightness controlling method.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 20, 2017
    Assignee: Pegatron Corporation
    Inventors: Ke-Ming Chen, Chien-Hua Huang
  • Publication number: 20170141104
    Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Publication number: 20170125340
    Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
  • Patent number: 9633999
    Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9627215
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hua Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Cherng-Shiaw Tsai
  • Publication number: 20170092580
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: CHIEN-HUA HUANG, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHERNG-SHIAW TSAI
  • Patent number: 9589890
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
  • Publication number: 20170053804
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 23, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao