Patents by Inventor Chien-Hua Huang

Chien-Hua Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9685138
    Abstract: A brightness controlling method for an all-in-one computer is provided. The all-in-one computer includes an on-screen display adjusting unit having a first brightness value, an operating system having a first system brightness value, a control unit and a scaler. The brightness controlling method includes the following steps. First, the first brightness value is adjusted to a second brightness value or the first system brightness value is adjusted to a second system brightness value. Then, when the first brightness value is adjusted to the second brightness value, the control unit synchronizes the first system brightness value to the second brightness value; when the first system brightness value is adjusted to the second system brightness value, the scaler adjusts the first brightness value to the second system brightness value. The invention also provides an all-in-one computer implementing the brightness controlling method.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 20, 2017
    Assignee: Pegatron Corporation
    Inventors: Ke-Ming Chen, Chien-Hua Huang
  • Publication number: 20170141104
    Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Publication number: 20170125340
    Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
  • Patent number: 9633999
    Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9627215
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hua Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Cherng-Shiaw Tsai
  • Publication number: 20170092580
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: CHIEN-HUA HUANG, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHERNG-SHIAW TSAI
  • Patent number: 9589890
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
  • Publication number: 20170053804
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 23, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 9558927
    Abstract: A method for reducing contaminants in a semiconductor device is provided. The method includes cleaning the semiconductor substrate. The cleaning includes rotating the semiconductor substrate and dispersing an aerosol at a predetermined temperature to a surface of the semiconductor substrate or a layer formed on the substrate to be cleaned. The aerosol includes a chemical having a predetermined pressure and a gas having a predetermined flow rate.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Tsung-Min Huang, Chung-Ju Lee
  • Publication number: 20170025346
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 26, 2017
    Inventors: Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
  • Patent number: 9490163
    Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hua Huang, Hsin-Chieh Yao, Chung-Ju Lee
  • Patent number: 9449839
    Abstract: The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A first self-assembled monolayer (SAM) layer is formed over the one or more layers, wherein the first SAM layer exhibits a first SAM pattern. At least a first of the one or more layers is patterned using the first SAM layer as a first etch mask to form first pillars in the first of the one or more layers and then removing the first SAM layer. A second self-assembled monolayer (SAM) layer is formed along sidewall portions of the first pillars after the first SAM layer has been removed, wherein the second SAM layer exhibits a second SAM pattern that differs from the first SAM pattern and where the second SAM layer differs in material composition from the first SAM layer.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Chien-Hua Huang
  • Publication number: 20160254166
    Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Chien-Hua Huang, Chung-Ju Lee
  • Patent number: 9418886
    Abstract: A method includes forming a patterned mask layer over a conductive layer; forming a first dielectric layer over the patterned mask layer and the conductive layer; selectively etching the first dielectric layer, thereby exposing an upper surface of the patterned mask layer, wherein the upper surface of the first dielectric layer is lower than a top surface of the patterned mask layer; removing the patterned mask layer; and selectively etching the conductive layer to form a conductive feature having a tapered profile.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hua Huang, Chieh-Han Wu, Chung-Ju Lee
  • Publication number: 20160225664
    Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.
    Type: Application
    Filed: January 25, 2016
    Publication date: August 4, 2016
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
  • Patent number: 9337055
    Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee
  • Patent number: 9245841
    Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Tsung-Min Huang
  • Publication number: 20150332625
    Abstract: A brightness controlling method for an all-in-one computer is provided. The all-in-one computer includes an on-screen display adjusting unit having a first brightness value, an operating system having a first system brightness value, a control unit and a scaler. The brightness controlling method includes the following steps. First, the first brightness value is adjusted to a second brightness value or the first system brightness value is adjusted to a second system brightness value. Then, when the first brightness value is adjusted to the second brightness value, the control unit synchronizes the first system brightness value to the second brightness value; when the first system brightness value is adjusted to the second system brightness value, the scaler adjusts the first brightness value to the second system brightness value. The invention also provides an all-in-one computer implementing the brightness controlling method.
    Type: Application
    Filed: April 22, 2015
    Publication date: November 19, 2015
    Inventors: Ke-Ming CHEN, Chien-Hua HUANG
  • Publication number: 20150137378
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9030697
    Abstract: The present invention discloses a printing device. The printing device of the present invention may include a communication element capable of communicating with an external host utilizing a plurality of telecommunication network technologies to receive a file sent from the external host to the device, a printing element electrically coupled to the communication element to output an image file, and an audio outputting element electrically coupled to the communication element to output an audio file, wherein the communication element identifies a file type of the file received from the external host and selectively sends the file to the printing element or the audio outputting element.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 12, 2015
    Assignee: HiTi Digital, Inc.
    Inventors: Chien-Hua Huang, Mei-Ju Ko, Jufen Huang, Chia-chen Wei, Hung-Chan Chien, Hong-Shun Chiou, Yu-Fan Fang, Chun-Chang Tu, Tsung-Yueh Chen, Chih-Chieh Lin, Yueh Cheng Lin, Shiu-Sheng Hsu, Chu-Ming Liu