Patents by Inventor Chien-Kang Chou

Chien-Kang Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190186897
    Abstract: A method for evaluating a leadframe surface includes positioning a leadframe on a measurement apparatus at a first predetermined distance relative to an end portion of a light source of an optical sensor; irradiating a predetermined area on a surface of the leadframe with light having a single predetermined wavelength from the light source; receiving, with a light receiver of the optical sensor, reflected light from the predetermined area on the surface of the leadframe, and converting the reflected light into an electric signal; determining a reflection intensity value of the predetermined area on the surface of the leadframe based on the electric signal; and calculating a reflection ratio of the predetermined area on the surface of the leadframe based on the reflection intensity value and a predetermined reference reflection intensity value associated with the light source.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Inventors: Hung-Yu CHOU, Chien-Hao WANG, Tse-Tsun CHIU, Fu-Kang LEE, Liang-Kang SU
  • Patent number: 8890336
    Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 18, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Jin-Yuan Lee, Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo
  • Patent number: 8884433
    Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 11, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8836146
    Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: September 16, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo
  • Patent number: 8723322
    Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: May 13, 2014
    Assignee: Megit Acquisition Corp.
    Inventors: Hsien-Tsung Liu, Chien-Kang Chou, Ching-San Lin
  • Patent number: 8692374
    Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: April 8, 2014
    Assignee: Megit Acquisition Corp.
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
  • Patent number: 8674507
    Abstract: A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: March 18, 2014
    Assignee: Megit Acquisition Corp.
    Inventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Chu-Fu Lin
  • Publication number: 20140007621
    Abstract: A method for manufacturing a polysilicon ingot includes: (a) providing molten silicon in a container; (b) maintaining a surface temperature of the molten silicon higher than its melting point while decreasing the temperature of a base portion of the container to a temperature (T1) lower than the melting point at a rate of at least 2.6° C./min; (c) increasing the temperature of the base portion to a temperature (T2) lower than the melting point; (d) maintaining the surface temperature of the molten silicon higher than the melting point while decreasing and then increasing the temperature of the base portion to a temperature lower than the melting point of silicon; and (e) reducing the temperature of the molten silicon to form the polysilicon ingot.
    Type: Application
    Filed: March 18, 2013
    Publication date: January 9, 2014
    Applicant: MOTECH INDUSTRIES INC.
    Inventors: Kai-An Ho, Chien-Kang Chou
  • Patent number: 8618580
    Abstract: An integrated circuit chip includes a semiconductor substrate, a first circuit in or coupled to the semiconductor substrate, a second circuit device in or coupled the semiconductor substrate, a dielectric structure coupled the semiconductor substrate, a first interconnecting structure in the dielectric structure, a first pad connected to the first node of the voltage regulator through the first interconnecting structure, a second interconnecting structure in the dielectric structure, a second pad connected to the first node of the analog circuit through the second interconnecting structure, a passivation layer coupled the dielectric structure, wherein multiple openings in the passivation layer exposes the first and second pads, and a third interconnecting structure coupled the passivation layer and coupled the first and second pads.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: December 31, 2013
    Assignee: Megit Acquisition Corp.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
  • Patent number: 8558383
    Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: October 15, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8461679
    Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: June 11, 2013
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo
  • Patent number: 8399989
    Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 19, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8373202
    Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: February 12, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
  • Patent number: 8362588
    Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: January 29, 2013
    Assignee: Megica Corporation
    Inventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
  • Patent number: 8319354
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
  • Patent number: 8304907
    Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 6, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8242601
    Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 14, 2012
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin
  • Patent number: 8198729
    Abstract: A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 ?m2.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: June 12, 2012
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Mou-Shiung Lin
  • Patent number: 8187965
    Abstract: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: May 29, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Michael Chen, Chien-Kang Chou, Mark Chou