Patents by Inventor Chien-Kuo Yang

Chien-Kuo Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030224545
    Abstract: A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 4, 2003
    Inventors: Steve S. Chung, Shang-Jr Chen, Chien-Kuo Yang, Der-Yuan Wu
  • Publication number: 20010020722
    Abstract: A step-like silicon on isolation (SOI) structure has a substrate, wherein isolation structures are located within the substrate and an active region is located between the isolation structures; a pair of source/drain regions formed within the active region; a channel region located between the source/drain regions and within the substrate; a gate structure located on the channel region and above the substrate; and a buried insulator layer located below the source/drain regions and the channel region, wherein the buried insulator layer is substantially conformal to the source/drain regions and the channel region and has a step-like profile.
    Type: Application
    Filed: March 28, 2001
    Publication date: September 13, 2001
    Inventor: Chien-Kuo Yang
  • Patent number: 6204129
    Abstract: A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: March 20, 2001
    Assignee: United Microelectronics Corp
    Inventors: Ching-Chun Hwang, Wei-Chung Chen, Chien-Kuo Yang