Abstract: A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane.

Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

Abstract: A polishing pad wear detecting apparatus suitable for a chemical mechanical polishing (CMP) apparatus is provided. The polishing pad wear detecting apparatus includes an arm and a height detector. One end of the arm is fastened on the CMP apparatus. The height detector is disposed on the arm for detecting height variation of a polishing pad.

Abstract: A chemical mechanical polishing (CMP) method is provided The method is capable of polishing a substrate in a CMP apparatus by using a hydrophobic polishing pad and includes following steps. A first CMP process is performed to the substrate. A first cleaning process is performed to the hydrophobic polishing pad. A second CMP process is performed to the substrate, wherein the first CMP process, the first cleaning process and the second CMP process are performed in sequence.

Abstract: A method of fabricating the semiconductor component including following steps is provided. A substrate is provided, wherein an opening is already formed in the substrate. A material layer is formed on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein. A sacrifice layer is formed on a surface of the recess. A chemical mechanical polishing (CMP) process is performed to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than that of the CMP process on the sacrifice layer.

Abstract: A membrane is suitable to be mounted on a polishing head of a chemical mechanical polishing apparatus and includes a main portion and an edge portion. The edge portion is located at an edge of the main portion, wherein a first included angle between the main portion and the edge portion is an obtuse angle.

Abstract: A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane.

Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.

Abstract: A method for forming a shallow trench isolation includes providing a substrate with a trench, a first liner layer and a second liner layer sequentially in the trench with a first oxide filling the trench, performing a first wet etching to remove part of the first oxide and part of the first liner layer to expose the substrate, performing a second wet etching to remove part of the second liner layer so that the second liner layer is lower than surface of the substrate, performing a third wet etching to remove part of the first oxide and part of the first liner layer, and filling the trench with a second oxide to form a shallow trench isolation.

Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.

Abstract: A method for forming a shallow trench isolation includes providing a substrate with a trench, a first liner layer and a second liner layer sequentially in the trench with a first oxide filling the trench, performing a first wet etching to remove part of the first oxide and part of the first liner layer to expose the substrate, performing a second wet etching to remove part of the second liner layer so that the second liner layer is lower than surface of the substrate, performing a third wet etching to remove part of the first oxide and part of the first liner layer, and filling the trench with a second oxide to form a shallow trench isolation.

Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

Abstract: The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

Abstract: The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

Abstract: A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact forming area is defined above the area between the two gate conductor stacks. A silicon dioxide lining film is deposited on a top surface and sidewalls of the gate conductor stacks. A sacrificing layer is deposited on the silicon dioxide lining film. The sacrificing layer is then polished to expose the top surface of the gate conductor stacks. A spin-on-glass (SOG) film is then coated on the sacrificing layer. A resist pattern masking the bit line contact forming area is formed on the SOG film. The un-masked SOG film, sacrificing layer and silicon dioxide lining film are etched away. A silicon nitride thin film is deposited on the remaining SOG film. A BPSG layer is deposited on the silicon nitride thin film and is then polished to expose the SOG layer.

Abstract: A method for forming a trench isolation structure. First, a substrate having at least one trench is provided. The trench is filled with a spin on glass (SOG) layer. Subsequently, a baking is performed on the SOG layer. The SOG layer is etched back to a predetermined depth. Next, a curing is performed on the remaining SOG layer. Finally, an insulating layer is formed on the remaining SOG layer to fill the trench completely.

Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.

Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.