Patents by Inventor Chien-Ming Lai

Chien-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120322218
    Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming LAI, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20120256276
    Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
  • Publication number: 20120154113
    Abstract: A wireless signal access apparatus receives wireless signals of IEEE 802.11 standard for controlling at least one appliance. The appliance may receive control signals of IEEE 802.15 standard, to be controlled according to the control signals. The wireless signal access apparatus receives the wireless signals having control data to generate the control signal of IEEE 802.15 standard, and send it to the appliance for omnidirectional remote control of the appliance.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 21, 2012
    Inventor: Chien-Ming Lai
  • Patent number: 8193050
    Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 5, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20120064679
    Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
    Type: Application
    Filed: November 25, 2011
    Publication date: March 15, 2012
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 8084824
    Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: December 27, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 7998818
    Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: August 16, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20110160319
    Abstract: An organic/inorganic hybrid composite proton exchange membrane is provided. The proton exchange membrane includes an inorganic material of about 0.5-30 parts by weight and an organic material of about 99.5-70 parts by weight per 100 parts by weight of the proton exchange membrane. A surface area of the inorganic material is about 50-3000 m2/g. The organic material includes a sulfonated polymer or a phosphoric acid doped polymer.
    Type: Application
    Filed: December 29, 2010
    Publication date: June 30, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Duan Tsai, Yong-Hong Liao, Shih-Wen Chen, Jiunn-Nan Lin, Chien-Ming Lai, Chiu-Ping Huang, Sung-Chun Chang
  • Patent number: 7932146
    Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: April 26, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wen Chen, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Tian-Fu Chiang, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20110076002
    Abstract: An image capturing device includes an image sensing unit, a shutter button mechanism, and a control unit. The image sensing unit includes a lens module and an image sensor. The shutter button mechanism is operable to generate a trigger signal when pressed and to generate a release signal when the shutter button mechanism is released after being pressed. The control unit is configured to perform, in response to the release signal from the shutter button mechanism, a picture taking procedure for controlling the image sensing unit to capture an image.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 31, 2011
    Inventor: Chien-Ming Lai
  • Patent number: 7888195
    Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
  • Publication number: 20110031558
    Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.
    Type: Application
    Filed: October 19, 2010
    Publication date: February 10, 2011
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20110034019
    Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20110018072
    Abstract: A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 27, 2011
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
  • Publication number: 20100317182
    Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.
    Type: Application
    Filed: August 25, 2010
    Publication date: December 16, 2010
    Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 7838946
    Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: November 23, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 7804141
    Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 7744741
    Abstract: The present invention provides a new method to obtain an effective diffusivity for a certain substance in solutions that diffuse through a porous material. The porous material initially separates two solutions that are different in concentration of the substance. The concentration gradient gives rise to diffusion through the porous material, The concentration change of the substance in the low-concentration compartment is detected through a measurement of the electrochemical impedance data. By means of the measurement, an effective diffusivity coefficient of the substance through the porous material is calculated.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: June 29, 2010
    Assignee: National Central University
    Inventors: Jing-Chie Lin, Chien-Ming Lai
  • Publication number: 20100059833
    Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 11, 2010
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
  • Publication number: 20100052074
    Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou