Patents by Inventor Chien-Pin Chan

Chien-Pin Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527504
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20220351983
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN
  • Patent number: 11417539
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Su-Fei Lin, Hsu-Lun Liu, Chien-Pin Chan, Yung-Sheng Lin
  • Publication number: 20210272819
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Application
    Filed: October 30, 2020
    Publication date: September 2, 2021
    Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10741513
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20190131263
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 2, 2019
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10163836
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20180166409
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: January 22, 2018
    Publication date: June 14, 2018
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 9875979
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20170141059
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 8952534
    Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang
  • Publication number: 20140070409
    Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen LAI, Chih-Kang HAN, Chien-Pin CHAN, Chih-Yuan CHIEN, Huai-Tei YANG
  • Patent number: 8610270
    Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang
  • Publication number: 20110193219
    Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: TAIWAN SEIMCONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen LAI, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang