Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: A method for producing a porous structure electrode with gas permeability and liquid impermeability, includes the following steps: Step 1: mixing a catalytic material having hydrophilicity, a carbon nanotube material, a material with a hydrophilic group, and a carbon black material to form a first slurry, wherein the carbon nanotube material has a specific surface area equal to or greater than the carbon black material; Step 2: mixing the first slurry with an emulsified material to form a second slurry; Step 3: obtaining a film material through a film forming process; Step 4: heating the film material to a first temperature to remove solvent in the film material; Step 5: Repeating steps 3 to 4; and Step 6: heating the film material to a second temperature to remove liquid in the film material, thereby leaving pores in the film material, and allowing the film material to solidify.

Abstract: The present invention provides a manufacturing method of an electrode. The method includes steps of: mixing a first catalyst with a first average particle size, a second catalyst with a second average particle size, a first conductive agent, a first adhesive, and a solvent to form a first mixture, wherein a weight ratio of the first catalyst to the second catalyst is 5:1 to 1:5; stirring the first mixture to obtain a second mixture; rolling the second mixture into a catalytic layer; and pressing the catalytic layer with a conductive current collector and a gas diffusion film to obtain the electrode.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Abstract: An integrated circuit (IC) device includes a plurality of first doped regions of a first semiconductor type over at least one first well region of the first semiconductor type, and a second doped region of a second semiconductor type over a second well region of the second semiconductor type. The second semiconductor type is different from the first semiconductor type. The plurality of first doped regions is arranged along a first direction. Each of the plurality of first doped regions has a first length in the first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.

Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

Abstract: A device for obtaining a newly generated oxygen from an atmospheric environment is disclosed. The device includes a container having an inlet and an outlet, a cathode accommodated in the container and being in contact with an environmental oxygen in the atmospheric environment, an anode accommodated in the container and disposed at a position opposite to the cathode, an electrolyte accommodated in the container and immersing therein the cathode and the anode, a moisture removal unit disposed at the outlet having an outlet position, and a gas permeable element disposed at the outlet, wherein the cathode is disposed at the inlet, and the gas permeable element is disposed at a position closer to the outlet position than the moisture removal unit.

Abstract: A method includes forming, over a substrate, a plurality of well taps arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps is arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps includes at least one first well tap. The forming the plurality of well taps comprises forming the first well tap by forming a first well region of a first type. The first well region comprises two first end areas and a first middle area arranged consecutively between the two first end areas in the second direction. The forming the first well tap further comprises implanting, in the first middle area, a first dopant of a first type, and implanting, in the first end areas, a second dopant of a second type different from the first type.

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.

Abstract: A semiconductor device includes a first well, a first region and fourth regions of a first conductivity type as well as second regions, a third region, a second well of the second conductivity type. A first region is disposed in the first well and coupled to a first reference voltage terminal. Second regions are disposed in the first well, wherein one of the second regions is coupled to the first reference voltage terminal, and the second regions and the first well are included in a first transistor. A third region is disposed in the first well. A first resistive load is coupled between the third region and a second reference voltage terminal. A second well is coupled to the first well. Fourth regions are disposed in the second well, wherein the second well and at least one of the fourth regions are included in a second transistor.

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: The invention provides a system for evaluating food flavors based on a gas, including a multi-gas sensing module and an odor information processing module. The sensing module includes a colorimetric gas sensing chip for reacting with odor molecules emitted by the food to be evaluated to form a coloring reaction, and the sensing module generates a color image respectively corresponding to coloring reaction according to the coloring reaction. The processing module is communicatively connected with the sensing module and includes an image acquisition unit for converting the color image into an odor information, a database unit including a plurality of identification information, and an arithmetic unit perform a calculation to form a result for evaluating the food flavors based on the plurality of identification information and the color image. The user can judge the actual condition of foods according to the result for evaluating the food flavors.

Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.

Abstract: The invention provides a system for managing food information based on an odor, which comprises a gas sensing module, a processing module, a blockchain module and a display module. The gas sensing module includes a colorimetric gas sensing chip reacting with odor molecules emitted by the food to form a coloring reaction and present a color image corresponding to the food. The processing module includes a conversion unit for converting the color image into identification information corresponding to the food. The blockchain module includes a plurality of nodes, and the plurality of nodes store identification information corresponding to the food. The display module includes an identification label corresponding to the identification information. Therefore, when the invention is applied to the blockchain technology, it can remove the doubt that the data on the chain can be falsified before the data is uploaded.

Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

Abstract: A living organism image monitoring system is provided, relating to the technical field of medical equipment. The living organism image monitoring system comprises a display module, a processor and a CIGS chip, the CIGS chip, the processor and the display module being electrically connected, the CIGS chip being used for detecting a near infrared light signal of a living organism and generating a current signal after having detected the near infrared light signal, the processor being used for generating a first pulse signal according to the current signal, and the display module being used for displaying an image according to the first pulse signal. The living organism image monitoring system provided by the present disclosure has the advantages of being capable of synchronously transmitting the images of a living organism to the display module for display and enabling the images to be clearer.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.

Abstract: A vending method capable of supporting vending machine with identity (ID) recognition function, suitable for a vending machine for verifying an identity of a consumer, and the method comprises steps of: generating a digital information on the vending machine; enabling an identity recognition application according to the digital information; enabling an image capture unit of a mobile device through the identity recognition application to capture a current head portrait of the consumer; and determining if the consumer passing through an identity recognition by using the identity recognition application; wherein, if the consumer passes through the identity recognition, enabling a sale function of the vending machine.