Abstract: A method includes forming a first conductive feature over a first semiconductor structure; forming a first dielectric layer over the first conductive feature and the first semiconductor structure; removing a portion of the first dielectric layer to expose a top surface of the first conductive feature; forming a second conductive feature over a second semiconductor structure, wherein the first and second conductive features comprise nanotwinned copper; forming a second dielectric layer over the second conductive feature and the second semiconductor structure, wherein the second dielectric layer comprises a same material as the first dielectric layer; removing a portion of the second dielectric layer to expose a top surface of the second conductive feature; and performing a hybrid bonding process to bond the first dielectric layer to the second dielectric layer and bond the first conductive feature to the second conductive feature.

Abstract: Fabricating a metal-insulator-metal (MIM) capacitor structure includes: forming a patterned metallization layer; disposing a dielectric material on the patterned metallization layer; etching one or more deep trenches through the dielectric material to the patterned metallization layer; depositing a MIM multilayer on the dielectric material and inside the one or more deep trenches formed in the dielectric material; and fabricating at least one three-dimensional MIM (3D-MIM) capacitor comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches; and fabricating at least one second capacitor, including at least one shallow 3D-MIM capacitor comprising a portion of the MIM multilayer deposited inside one or more shallow trenches passing partway through the dielectric material that are shallower than the one or more deep trenches, and/or at least one two-dimensional MIM (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material.

Abstract: An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.

Abstract: An image displacement device includes a first grating and a second grating. The first grating has a first surface and a second surface opposite the first surface, the first surface receives image beams, and the image beams leave the first grating by the second surface. The second grating is disposed downstream from the first grating in a light path and has a third surface and a fourth surface opposite the third surface. The third surface receives the image beams, and the image beams leave the second grating by the fourth surface. The image beams are projected to form a plane image comprised of pixels, each pixel is displaced in a direction by the image displacement device, and a displacement of each pixel is smaller than five times a width of one pixel.

Abstract: An immersion cooling system includes a tank, a first condenser, an enclosure, a second condenser and a connecting pipe. The tank has a first space. The first space is configured to accommodate a cooling liquid for at least one electronic equipment to immerse therein. The first condenser is disposed inside the tank. The enclosure is disposed outside the tank. The enclosure forms a second space together with the tank. The second condenser is disposed in the second space. The connecting pipe includes a first end and a second end opposite to the first end. The first end is connected with the second condenser. The second end is communicated with the first space.

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: A wearable device an intelligent health promotion service system (IHPSS) is disclosed. One embodiment of the wearable device (10) is configured to interface plurality groups of skin-mounted sensor pads (130) over a body part (140) of a wearer, and comprises: a modular brace (110) structurally separated from the sensor pads, and a plurality of sensor modules (120). The modular bracing is provided with a plurality groups of orienting slots (111) arranged thereon configured to maintain intra-group orientation between the sensor pads, and is configured to allow inter-group distance adjustment between the groups of the sensor pads over the body part of the wearer. The plurality of sensor modules is configured to be detachably coupled to the groups of sensor pads through the orienting slots in the modular bracing member. The sensor modules are provided with physiological sensing circuits wirelessly communicative with the intelligent health system.

Abstract: An apparatus for PVD is provided. The apparatus includes a chamber, a pedestal disposed in the chamber to accommodate a wafer, and a ring. The ring includes a ring body having a first top surface and a second top surface, and a barrier structure disposed between the first top surface and the second top surface. The barrier structure can further include at least a first portion and a second portion separated from each other. The second vertical distance is equal to or greater than the first vertical distance.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes affixing a spacer structure to a bottom side of a plurality of leads of a leadframe. A semiconductor die is attached to a top side of a die pad of the leadframe. The semiconductor die, the leadframe, and the spacer structure are encapsulated with an encapsulant. Portions of the spacer structure and portions of the leads of the plurality of leads are exposed at a bottom side of the encapsulant.

Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing a bounding volume hierarchy for a ray to arrive at a bounding box without use of a neural network; perform a feature vector lookup using modified polar coordinates characterizing the ray relative to the bounding box to obtain a set of feature vectors; and obtaining output with the neural network using the set of feature vectors.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a first wafer that includes multiple photonic dies. The method includes forming a second wafer that includes multiple electronic dies. The method includes forming micro lenses within the second wafer. The method includes bonding the first wafer to the second wafer after forming the plurality of micro lenses. The method further includes performing a singulation process to dice the first wafer and the second wafer to form multiple photonic packages, wherein one of the photonic packages includes an electronic die, a photonic die bonded to the electronic die, and one or more micro lenses embedded in the electronic die.

Abstract: A circulating current suppression method of a power system having a plurality of power modules is provided. Each power module includes a high-voltage bus, a low-voltage bus and a balance circuit having a neutral voltage. The circulating current suppression method includes: in each balance circuit, disposing a first capacitor electrically coupled between the high-voltage bus and the neutral voltage, and disposing a second capacitor electrically coupled between the neutral voltage and the low-voltage bus; acquiring a current effective value of an input of each power module; if detecting that the current effective value of at least one power module doesn't remain at a current reference value, determining that a circulating current occurs in the at least one power module; and operating the balance circuit of the at least one power module to charge the first capacitor or the second capacitor to regulate the neutral voltage for suppressing the circulating current.

Abstract: An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Abstract: A wavelength conversion element includes a rotatable disc, a first spoiler structure and a second spoiler structure. The rotatable disc has a supporting surface and a back surface opposite to the supporting surface. The first spoiler structure is disposed on the supporting surface and arranged along a first track surrounding a center of the rotatable disc. The second spoiler structure is disposed on the back surface and arranged along a second track surrounding the center. A centroid of at least one of the first spoiler structure and the second spoiler structure is deviated from the center. A projection device adopting the aforementioned wavelength conversion element is also provided. The wavelength conversion element of the invention can reduce the initial unbalance and the projection device of the invention can improve the durability.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.