Patents by Inventor Chih-Chang Lin

Chih-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200371152
    Abstract: An inspection apparatus including an illumination light source, a sensing probe and a processing device is provided. The illumination light source emits an illumination beam to simultaneously irradiate the plurality of light-emitting diode. The sensing probe is configured to measure a charge distribution, an electric field distribution, or a voltage distribution on the plurality of light-emitting diodes simultaneously irradiated by the illumination beam. The processing device determines a plurality of electro-optical characteristics of the plurality of light-emitting diodes through the charge distribution, the electric field distribution, or the voltage distribution on the plurality of light-emitting diodes simultaneously irradiated by the illumination beam. Moreover, a method of for inspecting light-emitting diodes is also provided.
    Type: Application
    Filed: June 19, 2020
    Publication date: November 26, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yan-Rung Lin, Chung-Lun Kuo, Chih-Hsiang Liu, Shie-Chang Jeng
  • Publication number: 20200350881
    Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Inventors: Chih-Wen Wu, Po Chang Lin, Chun Hua Tseng
  • Publication number: 20200345724
    Abstract: The present invention is directed to a depot composition for sustained release delivery of buprenorphine with enhanced stability and bioavailability. The composition is an injectable, low viscosity liquid and can form a depot in situ capable of delivering therapeutic level of buprenorphine over a period of time from one week to 3 months.
    Type: Application
    Filed: January 22, 2018
    Publication date: November 5, 2020
    Applicant: Foresee Pharmaceuticals Co., Ltd.
    Inventors: Yuhua LI, MingHsin LI, Chen-Chang LEE, Chia-Ying YANG, Chih-Ying LIN
  • Patent number: 10825918
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Publication number: 20200328208
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure also includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the first dummy fin structure, and a top surface of the capping layer is higher than a top surface of the first stacked structure and a top surface of the second stacked structure.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Publication number: 20200328169
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 10805611
    Abstract: A method and apparatus for video encoding or decoding used by a video encoder or decoder respectively. In one method, input data associated with a video sequence are received. A current sequence header for a current picture is determined. Whether the current sequence header corresponds to a first sequence header or a second sequence header is determined. If the current sequence header corresponds to the second sequence header, one or more syntax values of a syntax set associated with the first sequence header are assigned to corresponding one or more syntax values of the syntax set associated with the current sequence header. The current picture is then encoded or decoded according to the current sequence header.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 13, 2020
    Assignee: MediaTek Inc.
    Inventors: Min-Hao Chiu, Hsiu-Yi Lin, Chia-yun Cheng, Chih-Ming Wang, Yung-Chang Chang
  • Patent number: 10803115
    Abstract: An approach is provided to provide URLs based on a digital subject matter image (DSMI) received from a requestor. The approach identifies a set of classification labels pertaining to the DSMI and matches the set of classification labels against multiple sets of predefined labels with each of the sets of predefined labels corresponding to a URL. The matching results in a selected URL pertaining to the DSMI with this URL being returned to the requestor. In one embodiment, the approach is performed by a domain name system (DNS).
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Hsiung Liu, Cheng-Fang Lin, I-Chien Lin, Chiwen Chang, Ci-Wei Lan, Tsai-Hsuan Hsieh, Kate Lin, Peter Wu, Kuo-Liang Chou
  • Publication number: 20200321296
    Abstract: A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Inventors: Gulbagh SINGH, Chih-Ming LEE, Chi-Yen LIN, Wen-Chang KUO, C. C. LIU
  • Patent number: 10792904
    Abstract: A method for bonding a first component to a second component includes placing the first and second components in a cavity. Each of the first and second components has a bonding portion, and the bonding portion of the first component faces the bonding portion of the second component. A supercritical fluid is then introduced into the cavity with a temperature of 40-400° C. and a pressure of 1,500-100,000 psi, and a pressure of 4-100,000 psi is applied on both the first and second components, assuring the bonding portion of the first component bond to the bonding portion of the second component. Moreover, a method for separating a first component from a second component includes placing a composite in a cavity. The composite includes the first component, the second component and a connecting layer by which the first component joins to the second component. The supercritical is then introduced into the cavity.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 6, 2020
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Chih-Cheng Shih, Ming-Hui Wang, Wen-Chung Chen, Chih-Yang Lin
  • Patent number: 10787078
    Abstract: A touch knob which can transmit user touches above to a touch-sensitive surface below includes a base, a rotating shaft, and a rotating cap. The rotating cap defines a receiving groove facing the base, and the rotating shaft extends into the receiving groove and is connected to the rotating cap. The rotating cap is configured to rotate to transmit user touches in a bounded circular area, at least one conductive touch head is located on the rotating cap and in the receiving groove, and moves as the rotating cap moves. The disclosure avoids the need to cut or form any opening in the cover of the touch-sensitive surface or panel for buttons to be installed. A device using the above touch knob is also provided.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 29, 2020
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Nai-Hau Shiue, Yen-Heng Huang, Yen-Chang Yao, Li-Chun Hsu, Chih-Chiang Lin, Ya-Ting Chang, Yen-Hsun Chen
  • Publication number: 20200303194
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a substrate, a fin structure formed over the substrate, and an isolation structure formed over the substrate. The fin structure protrudes from the isolation structure. The FinFET device structure further includes a fin isolation structure formed over the isolation structure and a metal gate structure formed over the fin structure and the fin isolation structure.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Ni YU, Zhi-Chang LIN, Wei-Hao WU, Huan-Chieh SU, Chung-Wei HSU, Chih-Hao WANG
  • Publication number: 20200303366
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
  • Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • Patent number: 10778203
    Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Chun Yang, Chih-Chang Lin, Ming-Chieh Huang
  • Publication number: 20200287574
    Abstract: A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.
    Type: Application
    Filed: January 30, 2020
    Publication date: September 10, 2020
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20200287528
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10770570
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Publication number: 20200279934
    Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chih-Han Lin, Shih-Chang TSAI, Wen-Shuo HSIEH, Te-Yung LIU
  • Patent number: 10764475
    Abstract: A driving mechanism is provided, including a housing, a hollow frame, a holder, and a driving assembly. The frame is fixed to the housing and has a stop surface. The holder is movably disposed in the housing for holding the optical element. The driving assembly is disposed in the housing to drive the holder and the optical element moving along the optical axis of the optical element relative to the frame. Specifically, the stop surface is parallel to the optical axis to contact the holder and restrict the holder in a limit position.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu