Patents by Inventor Chih-Chang Lin

Chih-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299756
    Abstract: A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Patent number: 11714239
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Patent number: 11677388
    Abstract: A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Tien-Chun Yang
  • Publication number: 20230111170
    Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 13, 2023
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Min-Hsiang Hsu, Weiwei Song, Chewn-Pu Jou, Feng-Wei Kuo, Huan-Neng Chen, Lan-Chou Cho
  • Publication number: 20230105446
    Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei SONG, Chan-Hong CHERN, Chih-Chang LIN, Stefan RUSU, Min-Hsiang HSU
  • Patent number: 11531159
    Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chan-Hong Chern, Lan-Chou Cho, Huan-Neng Chen, Min-Hsiang Hsu, Feng-Wei Kuo, Chih-Chang Lin, Weiwei Song, Chewn-Pu Jou
  • Patent number: 11525957
    Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei Song, Chan-Hong Chern, Chih-Chang Lin, Stefan Rusu, Min-Hsiang Hsu
  • Publication number: 20220357518
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Publication number: 20220342239
    Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.
    Type: Application
    Filed: July 19, 2021
    Publication date: October 27, 2022
    Inventors: Weiwei Song, Stefan Rusu, Chan-Hong Chern, Chih-Chang Lin
  • Publication number: 20220328707
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, a first doped region having a first conductivity type at a first side of the photosensitive member, wherein the first doped region is in the silicon layer, and a second doped region having a second conductivity type different from the first conductivity type at a second side of the photosensitive member opposite to the first side, wherein the second doped region is in the silicon layer, and the first doped region is apart from the second doped region, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 13, 2022
    Inventors: CHAN-HONG CHERN, WEIWEI SONG, CHIH-CHANG LIN, LAN-CHOU CHO, MIN-HSIANG HSU
  • Patent number: 11448828
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Publication number: 20220269006
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Patent number: 11393939
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chan-Hong Chern, Weiwei Song, Chih-Chang Lin, Lan-Chou Cho, Min-Hsiang Hsu
  • Publication number: 20220100007
    Abstract: A directional coupler is configured to receive a continuous light waveform and split the waveform into two carrier signals. Ring modulators are configured to receive the carrier signals and binary data and modulate the carrier signals based on the binary data. A combiner is configured to combine the modulated carrier signals into a four-level pulse amplitude modulation (PAM4) signal.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Chih-Chang LIN, Chan-Hong CHERN
  • Publication number: 20210396930
    Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
    Type: Application
    Filed: March 25, 2021
    Publication date: December 23, 2021
    Inventors: Chan-Hong Chern, Lan-Chou Cho, Huan-Neng Chen, Min Hsiang Hsu, Feng-Wei Kuo, Chih-Chang Lin, Weiwei Song, Chewn-Pu Jou
  • Publication number: 20210302650
    Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei SONG, Chan-Hong Chern, Chih-Chang Lin, Stefan Rusu, Min-Hsiang Hsu
  • Patent number: 11128285
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20210137328
    Abstract: An automatic cleaning apparatus is configured to clean a floor and emit ultraviolet light for sterilizing the floor in a cleaning mode. Upon detecting that a wall is nearby, the automatic cleaning apparatus emits ultraviolet light toward a corner formed by the floor and the wall for sterilization.
    Type: Application
    Filed: May 21, 2020
    Publication date: May 13, 2021
    Applicant: NKFG Corporation
    Inventors: Te-Li TIEN, Shao-Wei CHIU, Yu-De LIN, Hsiang-En CHIU, Han-Chien CHENG, Chih-Chang LIN
  • Publication number: 20210091245
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.
    Type: Application
    Filed: July 6, 2020
    Publication date: March 25, 2021
    Inventors: CHAN-HONG CHERN, WEIWEI SONG, CHIH-CHANG LIN, LAN-CHOU CHO, MIN-HSIANG HSU
  • Patent number: 10921891
    Abstract: Systems and methods for authentication code entry in touch-sensitive screen enabled devices are disclosed. In one embodiment, a method for entering authentication value data to a data entry device that comprises at least one computer processor and a touch-sensitive screen may include: (1) the touch-sensitive screen sensing a control touch on the touch-sensitive screen; (2) the touch-sensitive screen sensing a release of the control touch from the touch-sensitive screen; (3) the at least one computer processor determining a number of first touches sensed by the touch-sensitive screen in a period between the sensing of the control touch and the sensing of the release of the control touch; and (4) the at least one computer processor using the number of first touches to represent a value in an authentication code.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 16, 2021
    Assignee: VeriFone, Inc.
    Inventors: Chih-Chang Lin, Chan He Lin