Patents by Inventor Chih-Cherng Liao

Chih-Cherng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240274726
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxial layer, a well region, an insulating structure, an upper electrode layer, and a lower electrode layer. The substrate has the first conductivity type. The epitaxial layer is disposed on the substrate and has the first conductivity type. There is a protruding structure on the upper portion of the epitaxial layer. The well region is disposed in the epitaxial layer. The well region has the second conductivity type. The insulating structure is disposed on the sidewall of the protruding structure. The upper electrode layer surrounds the protruding structure and is electrically connected to the epitaxial layer and the well region. The lower electrode layer is disposed under the substrate and opposite to the epitaxial layer.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 15, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chen-Dong TZOU, Yun-Kai LAI, Chih-Cherng LIAO, Chia-Hao LEE
  • Publication number: 20240222494
    Abstract: A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer on the substrate and having the first conductivity type, a trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, and a well region extending into the epitaxial layer and has the second conductivity type. The first sidewall of the well region is in contact with the trench structure. The trench structure includes a conductive portion and an insulating layer that covers the sidewalls and the bottom portion of the conductive portion. A drift region that has the first conductivity type is adjacent to and under the well region. The drift region is in contact with the second sidewall and the bottom surface of the well region. The semiconductor device further includes a gate structure on the top surface of the epitaxial layer and over the well region.
    Type: Application
    Filed: January 4, 2023
    Publication date: July 4, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chen-Dong TZOU, Chih-Cherng LIAO, Chien-Hsien SONG, Chia-Hao LEE, Tzu-Hsuan CHEN
  • Publication number: 20240194669
    Abstract: A semiconductor device includes a compound semiconductor channel layer disposed on a substrate and located in an active element region and a passive element region. A compound semiconductor barrier layer is stacked on the compound semiconductor channel layer and located in the active element region and the passive element region. A source electrode, a gate electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located in the active element region to construct a high electron mobility transistor. In addition, a first terminal electrode, an intermediate electrode and a second terminal electrode are disposed on the compound semiconductor barrier layer and located in the passive element region to construct a resistor.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 13, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao Lee, Chih-Cherng Liao, Po-Heng Lin
  • Publication number: 20240097050
    Abstract: A semiconductor device includes a trench disposed in an epitaxial layer on a substrate. A gate structure is disposed in the trench and includes upper and lower conductive portions. A dielectric isolation portion is disposed between the upper and lower conductive portions. A dielectric liner is disposed in the trench and has an opening on the bottom surface of the trench. The opening is filled up with a part of the lower conductive portion. A portion of the epitaxial layer and the lower conductive portion construct a Schottky barrier diode. A doped region is disposed in the epitaxial layer, under the bottom surface of the trench and on one side of the lower conductive portion. The portion of the epitaxial layer and a portion of the doped region are in contact with the lower conductive portion.
    Type: Application
    Filed: September 18, 2022
    Publication date: March 21, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chen-Dong Tzou, Chih-Cherng Liao, Chia-Hao Lee
  • Publication number: 20240096987
    Abstract: A semiconductor device includes an epitaxial layer, at least one gate trench, and at least one trench gate structure. The gate trench includes a lower gate trench and an upper gate trench, and a width of the lower gate trench is less than a width of the upper gate trench. The trench gate structure is disposed in the gate trench, and the trench gate structure includes a bottom gate structure, a middle gate structure, and a top gate structure. The thickness of the second gate dielectric layer of the middle gate structure is less than the thickness of the first gate dielectric layer of the bottom gate structure. The thickness of the third gate dielectric layer of the top gate structure is less than the thickness of the second gate dielectric layer of the middle gate structure. The first, second, and third gate electrodes are separated from each other.
    Type: Application
    Filed: September 18, 2022
    Publication date: March 21, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Syed-Sarwar Imam, Chih-Cherng Liao, Chia-Hao Lee
  • Publication number: 20240047460
    Abstract: A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng Liao, Chung-Ren Lao, Hsing-Chao Liu, Chun-Wei Li, Hsueh-Chun Liao
  • Patent number: 11742389
    Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: August 29, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hung-Chih Tan, Hsing-Chao Liu, Chih-Cherng Liao, Hsiao-Ying Yang, Kai-Chuan Kan, Jing-Da Li
  • Patent number: 11637139
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: April 25, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Chih-Cherng Liao, Shih-Hao Liu, Wu-Hsi Lu, Ming-Cheng Lo, Wei-Lun Chung, Chih-Wei Lin
  • Patent number: 11569121
    Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 31, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: I-Ping Lee, Kwang-Ming Lin, Chih-Cherng Liao, Ya-Huei Kuo, Pei-Yu Chang, Ya-Ting Chang, Tsung-Hsiung Lee, Zheng-Xian Wu, Kai-Chuan Kan, Yu-Jui Chang, Yow-Shiuan Liu
  • Patent number: 11538840
    Abstract: A semiconductor device includes a conductive substrate and an encapsulation structure. The conductive substrate has a plurality of pixels. The encapsulation structure is disposed on the conductive substrate and includes at least one light-collimating unit. The light-collimating unit includes a transparent substrate and a patterned light-shielding layer. The patterned light-shielding layer is disposed on the transparent substrate. The patterned light-shielding layer has a plurality of holes disposed to correspond to the pixels.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 27, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wu-Hsi Lu, Chung-Ren Lao, Chih-Cherng Liao, Shih-Hao Liu, Ming-Cheng Lo, Wei-Lun Chung
  • Publication number: 20220384251
    Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: I-Ping LEE, Kwang-Ming LIN, Chih-Cherng LIAO, Ya-Huei KUO, Pei-Yu CHANG, Ya-Ting CHANG, Tsung-Hsiung LEE, Zheng-Xian WU, Kai-Chuan KAN, Yu-Jui CHANG, Yow-Shiuan LIU
  • Publication number: 20220376052
    Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hung-Chih TAN, Hsing-Chao LIU, Chih-Cherng LIAO, Hsiao-Ying YANG, Kai-Chuan KAN, Jing-Da LI
  • Patent number: 11436992
    Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 6, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung Chin, Ching-Yi Hsu, Chang-He Liu, Chih-Cherng Liao, Jun-Wei Chen, Leuh Fang
  • Publication number: 20220238584
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.
    Type: Application
    Filed: April 13, 2022
    Publication date: July 28, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Chih-Cherng Liao, Shih-Hao Liu, Wu-Hsi Lu, Ming-Cheng Lo, Wei-Lun Chung, Chih-Wei Lin
  • Patent number: 11393921
    Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: July 19, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hung-Chih Tan, Hsing-Chao Liu, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 11387361
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu Huang, Tse-Hsiao Liu, Pao-Hao Chiu, Chih-Cherng Liao, Ching-Yi Hsu
  • Publication number: 20220216308
    Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 11374096
    Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: June 28, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 11335717
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 17, 2022
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Chih-Cherng Liao, Shih-Hao Liu, Wu-Hsi Lu, Ming-Cheng Lo, Wei-Lun Chung, Chih-Wei Lin
  • Publication number: 20220069122
    Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Inventors: Hung-Chih Tan, Hsing-Chao Liu, Hsiao-Ying Yang, Chih-Cherng Liao