Abstract: An evolved NodeB eNB, a first relay node (RN) and a connection initialization method thereof for use in a long term evolution (LTE) network are provided. The LTE network comprises the eNB, the first RN, a second RN and a mobility management entity (MME). In the LTE network of the present invention, various multi-hop protocols can be achieved by using different identification mapping implementations.

Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

Abstract: The present invention relates to a resource allocation apparatus, subscriber station, resource allocation method, and non-transitory computer readable medium thereof. The resource allocation apparatus may know the unoccupied partition of the wireless network resource and allocate the unoccupied partition to the SS of the femtocell network. Thereby, the SS of the femtocell network will not occupy the same network resource of the macro BS or other femto SS, and interference of between femtocell and macrocell or other femtocell is reduced effectively.

Abstract: An evolved NodeB eNB, a first relay node (RN) and a connection initialization method thereof for use in a long term evolution (LTE) network are provided. The LTE network comprises the eNB, the first RN, a second RN and a mobility management entity (MME). In the LTE network of the present invention, various multi-hop protocols can be achieved by using different identification mapping implementations.

Abstract: Wireless communication apparatuses, header compression methods thereof, and header decompression method thereof are provided. The header compression method enables the transceiver to establish a tunnel for a user equipment, enables the processing unit to receive a first packet, enables the processing unit to generate a second packet comprising an outer header set and the first packet, enables the processing unit to replace the outer header set of the second packet with a replaced header, and enables the transceiver to transmit the second packet by the tunnel according to an identity recorded in the replaced header. The header decompression method decompresses the header compressed by the header compression method.

Abstract: A relay station and a backhaul connection method thereof are provided. The relay station adopts an NAS mechanism. A wireless communication system comprises the relay station, a base station, and a core network. The relay station comprises a processing unit and a transceiver. The processing unit enters a first state of the NAS mechanism after the relay station creates a radio connection with the core network. The transceiver transmits a backhaul connection request to the base station after the relay station enters the first state. The processing unit then enters a second state of the NAS mechanism after the transmission of the backhaul connection request. The transceiver then receives a backhaul connection response from the base station after the transmission of the backhaul connection request. The processing unit then enters the first state after the receipt of the backhaul connection response.

Abstract: A base station and an attaching method thereof are provided. A relay network system comprises the base station, a relay station and a core network. The base station is connected with the core network via a backhaul link. The base station comprises a processing unit and a transceiver. The processing unit is configured to setup a communication link procedure between the relay station and the core network corresponding to a link request from the relay station, and to create a mapping table for connecting the relay station and the core network. The transceiver is configured to forward network packets and control signals between the relay station and the core network based on the mapping table.

Abstract: A relay station and a backhaul control communication thereof are provided. A wireless communication system comprises the relay station, a base station, and a core network. The relay station is wirelessly connected to the base station, while the base station is wiredly connected to the core network. The relay station comprises a processing unit and a transceiver. The processing unit is configured to create a radio link having a control plane connection between the relay station and the base station and create a backhaul link between the relay station and the base station by the control plane connection of the radio link. The transceiver is configured to transmit a backhaul control message to the core network via the backhaul link.

Abstract: A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

Abstract: The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed in the semiconductor substrate adjacent to the gate, and then an epitaxial layer is formed in the recess. A lightly doped region is formed in the semiconductor substrate adjacent to the gate. Finally, a spacer is formed on the sidewall of the gate.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

Abstract: The retractable cable device includes a base, a rotary portion, a spring, a cover, and at least two medal plates. The rotary portion cooperates with the base to form a cavity, and the cable is disposed on the rotary portion. The spring is disposed in the cavity for driving the rotary portion to rotate. The cover is coupled to the base. The metal plate is connected to the rotary portion for maintaining an electrical connection between the antenna and the cable when the rotary portion rotates.

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.

Abstract: A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar.

Abstract: The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed in the semiconductor substrate adjacent to the gate, and then an epitaxial layer is formed in the recess. A lightly doped region is formed in the semiconductor substrate adjacent to the gate. Finally, a spacer is formed on the sidewall of the gate.

Abstract: A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and a second process after the first process. The method includes forming a silicon nitride layer in the recess along the profile of the same during the second process.