Patents by Inventor Chih-Hong Hwang
Chih-Hong Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240222377Abstract: A semiconductor device includes a plurality of nanostructures over a substrate arranged in a z-axis and a gate stack wrapping around the plurality of nanostructures. Thea gate stack comprises a gate dielectric layer and a p-type work function material on the gate dielectric layer. The gate dielectric layer wraps around the plurality of nanostructures. The p-type work function material has a first thickness along the z-axis above a topmost one of the plurality of nanostructures and a second thickness along the z-axis between neighboring two of the plurality of nanostructures, and the first thickness is less than the second thickness.Type: ApplicationFiled: January 3, 2023Publication date: July 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Che-Chia HSU, Chih-Pin TSAO, Chih-Hong HWANG, Shih-Hsun CHANG
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Publication number: 20240204073Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a first channel structure and a second channel structure and forming a first type of source/drain structures attached to opposite sides of the first channel structure and a second type of source/drain structures attached to opposite sides of the second channel structure. The method also includes forming a first gate dielectric layer having a first portion covering the first channel structure and a second portion covering the second channel structure and driving a first metal element into the first portion of the first gate dielectric layer. The method also includes forming a cap layer over both the first portion and the second portion of the first gate dielectric layer and performing an annealing process on the first gate dielectric layer under the cap layer.Type: ApplicationFiled: February 2, 2023Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi HUANG, Che-Chia HSU, Chih-Pin TSAO, Chih-Hong HWANG
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Publication number: 20240055522Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. The method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. The top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
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Patent number: 11837663Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.Type: GrantFiled: August 2, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
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Publication number: 20210359127Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.Type: ApplicationFiled: August 2, 2021Publication date: November 18, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
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Patent number: 11081585Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.Type: GrantFiled: June 22, 2020Date of Patent: August 3, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
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Publication number: 20200321460Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
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Patent number: 10693004Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.Type: GrantFiled: October 18, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufactruing Co., Ltd.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
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Publication number: 20200058785Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.Type: ApplicationFiled: October 18, 2018Publication date: February 20, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
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Patent number: 9865429Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.Type: GrantFiled: November 14, 2014Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hong Hwang, Chun-Lin Chang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9805913Abstract: A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.Type: GrantFiled: June 2, 2015Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hong Hwang, Chun-Lin Chang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9449889Abstract: A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a first sensor and a second sensor simultaneously with the wafer holder, receiving a first sensed signal and a second sensed signal from the first sensor and the second sensor respectively and adjusting an ion beam generated by an ion beam generator based upon the first sensed signal and the second sensed signal.Type: GrantFiled: April 13, 2015Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Chang, Chih-Hong Hwang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9330901Abstract: A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %).Type: GrantFiled: March 1, 2013Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: An-Chun Tu, Chih-Hong Hwang, Yi Hsien Lu, Chun-Heng Chen, Chen-Chien Li, Chih-Jen Wu, Kuei-Shu Chang-Liao, Chen-Ming Huang
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Publication number: 20150270103Abstract: A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.Type: ApplicationFiled: June 2, 2015Publication date: September 24, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hong HWANG, Chun-Lin CHANG, Nai-Han CHENG, Chi-Ming YANG, Chin-Hsiang LIN
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Publication number: 20150221561Abstract: A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a first sensor and a second sensor simultaneously with the wafer holder, receiving a first sensed signal and a second sensed signal from the first sensor and the second sensor respectively and adjusting an ion beam generated by an ion beam generator based upon the first sensed signal and the second sensed signal.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: Chun-Lin Chang, Chih-Hong Hwang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9070534Abstract: A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.Type: GrantFiled: May 4, 2012Date of Patent: June 30, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hong Hwang, Chun-Lin Chang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9053907Abstract: An apparatus comprises a plasma flood gun for neutralizing a positive charge buildup on a semiconductor wafer during a process of ion implantation using an ion beam. The plasma flood gun comprises more than two arc chambers, wherein each arc chamber is configured to generate and release electrons into the ion beam in a respective zone adjacent to the semiconductor wafer.Type: GrantFiled: April 4, 2012Date of Patent: June 9, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Chang, Chih-Hong Hwang, Wen-Yu Ku, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9031684Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.Type: GrantFiled: November 1, 2011Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
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Patent number: 9006676Abstract: An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second sensor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second sensor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer.Type: GrantFiled: June 14, 2013Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Chang, Chih-Hong Hwang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Publication number: 20150069913Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Chih-Hong Hwang, Chun-Lin Chang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin