Abstract: A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

Abstract: A multiple layer metal interconnect process provides for both good electrical properties and good mechanical properties by using a first extremely low k dielectric material at the lower level metal layers, a second extremely low k dielectric material at the middle level metal layers, and a low k dielectric material at the upper level metal layers.

Abstract: A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.

Abstract: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.

Abstract: A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.

Abstract: A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.

Abstract: A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process water; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.

Abstract: The present invention provides two or more test structures/substructures (100) that are used in a test pattern (500, 600, 700, 800) to determine a cracking threshold for a dielectric material (104) on a substrate. Each test structure/substructure (100) includes two metal structures (102) separated by the dielectric material (104) having a width (G) which is different for each test structure/substructure (100). The cracking threshold will be approximately equal to the largest width (G) of dielectric material (104) that is cracked after processing. The present invention also provides a method for determining the cracking threshold for the dielectric material (104). Two or more test structures (100) are formed on the substrate (402) followed by a determination of whether the dielectric material (104) between the two metal structures (102) for each test structure (100) has cracked during processing (404).

Abstract: A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.

Abstract: A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.

Abstract: A method for reducing electrical discharges within semiconductor wafers including providing a semiconductor process wafer comprising at least one dielectric insulating layer including metal interconnects; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates within portions of the semiconductor process wafer; and, limiting the semiconductor process wafer to exposure of visible light comprising wavelengths greater than a predetermined lower limit for a period of time prior to carrying out a subsequent process to reduce a level of photo-currents generated within the semiconductor process wafer.

Abstract: A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.