Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.

Abstract: A sprayer, comprising: a container, configured to contain liquid; a passage, comprising a first opening, a second opening, a resonator and a mesh, when the liquid is passed through the resonator, the liquid is emitted as a gas; a first optical sensor, configured to sense first optical data of at least portion of the mesh or at least portion of a surface of the container; and a processing circuit, configured to compute a foaming level of the mesh or of the surface according to the first optical data, and configured to determine whether the resonator should be turned off or not according to the foaming level. In another aspect, the processing circuit estimates a liquid level of the liquid but does not correspondingly turn off the resonator. By this way, the resonator may be turned on or turned off more properly and the liquid level may be more precisely estimated.

Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.

Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC includes a processor of the SoC including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus, the deadlock controller being configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and extract, via the second bus, state information of the isolated processor in the deadlock state.

Abstract: The present invention relates to the technical field of a barbecue utensil and discloses a barbecue grill including a barbecue grill body having a cavity with an opening in an upper end, a heating furnace head and a hot plate are disposed in the cavity, and a barbecue wire mesh is disposed on the opening of the cavity, the hot plate covers the whole top of the heating furnace head and is provided with a plurality of ventilation holes, and an upper surface of the hot plate is inclined and is provided with a plurality of covering plates on the positions corresponding to the ventilation holes, each covering plate covers the whole top of the ventilation hole, one end of the covering plate is connected to an upper surface of the hot plate and the other end extends slantwise downwards and a gap is disposed between the upper surface of the hot plate and the other end of the covering plate.

Abstract: A computer system maintains a threshold value, wherein the threshold value indicates a period of time. The computer system determines that a processor is in any one of a plurality of low power consumption states. Responsive to a determination that the processor is in any one of the plurality of low power consumption states, the computer system increments a counter. The counter indicates the period of time the processor has been in any one of the plurality of low power consumption state. The computing system determines that the counter value is equal to or greater than the threshold value. Responsive to a determination that the counter value is equal to or greater than the threshold value, the computer system sends a first indication to a memory module indicating to the memory module to reduce the memory module refresh rate.

Abstract: A barbecue grill includes a body, a support and a platform frame. The body is mounted in the support, and the support is erected on the platform frame. The body defines an oven chamber. An oil discharge port is arranged at a bottom of the oven chamber. A plurality of keys are arranged near an opening on the inner sidewall of the oven chamber. A barbecue plate is arranged in the body, and the edge of the barbecue plate rests on the plurality of keys. A burner is arranged in the body, and is located below the barbecue plate. The platform frame includes an oven platform and a stand mounted at the bottom of the oven platform. The support is erected on the oven platform. The oven platform defines a groove for placement of the barbecue plate. A slot is defined on the oven platform to support legs.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.

Abstract: A barbecue grill includes an oven, a supporting member, and a pair of holders. The supporting member includes a panel, a first stand, and a second stand in cross connection with the first stand and pivoting on the first stand. One end of the first stand pivots on a bottom of the panel, and one end of the second stand is fixed with the bottom of the panel. The pair of holders support the oven, one end of each of the pair of holders pivots on a bottom of the oven, and another end of each of the pair of holders is fixed on the supporting member. When the pair of holders are detached from the panel, the pair of holders stack on the bottom of the oven, and when the second stand is detached from the panel, the second stand and the panel stack on the first stand.

Abstract: A computer system maintains a threshold value, wherein the threshold value indicates a period of time. The computer system determines that a processor is in any one of a plurality of low power consumption states. Responsive to a determination that the processor is in any one of the plurality of low power consumption states, the computer system increments a counter. The counter indicates the period of time the processor has been in any one of the plurality of low power consumption state. The computing system determines that the counter value is equal to or greater than the threshold value. Responsive to a determination that the counter value is equal to or greater than the threshold value, the computer system sends a first indication to a memory module indicating to the memory module to reduce the memory module refresh rate.