Patents by Inventor Chih-Liang Chen

Chih-Liang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366844
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Publication number: 20210358848
    Abstract: An integrated circuit includes a first power rail, a second power rail, a signal line and a first active region of a first set of transistors. The first power rail is on a back-side of a substrate, and extends in a first direction. The second power rail is on the back-side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back-side of the substrate, and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first set of transistors extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side.
    Type: Application
    Filed: March 9, 2021
    Publication date: November 18, 2021
    Inventors: Guo-Huei WU, Pochun WANG, Wei-Hsin TSAI, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20210358847
    Abstract: A semiconductor device, includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as a ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.
    Type: Application
    Filed: December 1, 2020
    Publication date: November 18, 2021
    Inventors: Chih-Liang CHEN, Guo-Huei WU, Li-Chun TIEN
  • Patent number: 11177397
    Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 16, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Hui Lee, Han-Liang Tseng, Jiunn-Liang Yu, Kwang-Ming Lin, Yin Chen, Si-Twan Chen, Hsueh-Jung Lin, Wen-Chih Lu, Chih-Hsien Chen
  • Patent number: 11177179
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
  • Publication number: 20210343715
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Guo-Huei WU, Jerry Chang-Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
  • Publication number: 20210343646
    Abstract: A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.
    Type: Application
    Filed: February 4, 2021
    Publication date: November 4, 2021
    Inventors: Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20210338414
    Abstract: A tissue repair device and a method for using the same are provided. The tissue repair device includes a body portion and at least one wire. The body portion includes an inner layer and an outer layer. The inner layer is close to a tissue, wherein the inner layer includes a hydrophilic structure, and the outer layer includes a hydrophobic structure. The wire is connected to the body portion to fix the body portion to the tissue.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Chieh HUANG, Jeng-Liang KUO, Hui-Ting HUANG, Shiun-Yin CHANG, Meng-Hsueh LIN, Cheng-Yi WU, Lih-Tao HSU, Pei-I TSAI, Hsin-Hsin SHEN, Chih-Yu CHEN, Kuo-Yi YANG, Chun-Hsien MA
  • Patent number: 11158509
    Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Publication number: 20210328501
    Abstract: The present invention discloses a power converter controller having a short-circuit protection threshold voltage no higher than an over-current protection threshold voltage so that any abnormal voltage or current stress on semiconductor components can be timely sensed via a current sense pin in the event of a short-circuit fault, effectively preventing semiconductor components from being damaged.
    Type: Application
    Filed: August 14, 2020
    Publication date: October 21, 2021
    Inventors: Chin-Chuan Chen, Shu-Chia Lin, Chih-Liang Wang, Kuo-Jung Wu
  • Publication number: 20210328502
    Abstract: The present invention discloses a power converter controller with short-circuit protection employing a short-circuit protection increasing slope threshold no higher than an over-current protection increasing slope threshold to detect a short-circuit abnormality in advance through a current sensing pin while any semiconductor component suffering from abnormal voltage or over-current, thereby preventing the semiconductor components from damage.
    Type: Application
    Filed: August 14, 2020
    Publication date: October 21, 2021
    Inventors: Chin-Chuan Chen, Shu-Chia Lin, Chih-Liang Wang
  • Patent number: 11145678
    Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jack Liu, Jiann-Tyng Tzeng, Chih-Liang Chen, Chew-Yuen Young, Sing-Kai Huang, Ching-Fang Huang
  • Publication number: 20210313972
    Abstract: An input circuit of a flip-flop includes: a first gate strip, a second gate strip and a third gate strip. The first gate strip is a co-gate terminal of a first PMOS and a first NMOS; the second gate strip is disposed immediately adjacent to the first gate strip, and a co-gate terminal of a second PMOS and a second NMOS. The first PMOS and the second PMOS share a doping region as a co-source terminal. The first NMOS and the second NMOS share a doping region as a co-source terminal. The third gate strip is disposed immediately adjacent to the second gate strip. The third gate strip is a co-gate terminal of a third PMOS and a third NMOS. The second PMOS and the third PMOS share a doping region as a co-drain terminal. The second NMOS and the third NMOS share a doping region as a co-drain terminal.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: JIN-WEI XU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN
  • Patent number: 11133255
    Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20210288149
    Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 16, 2021
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20210288150
    Abstract: A high-electron mobility transistor includes a substrate, a GaN channel layer over the substrate, an AlGaN layer over the GaN channel layer, a gate recess in the AlGaN layer, a source region and a drain region on opposite sides of the gate recess, a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively, a p-GaN gate layer in and on the gate recess; and a re-grown AlGaN film on the AlGaN layer, on the GaN source layer and the GaN drain layer, and on interior surface of the gate recess.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 16, 2021
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11121256
    Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Liang Chen, Lei-Chun Chou, Jack Liu, Kam-Tou Sio, Hui-Ting Yang, Wei-Cheng Lin, Chun-Hung Liou, Jiann-Tyng Tzeng, Chew-Yuen Young
  • Publication number: 20210280607
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20210272895
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Patent number: 11107805
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Sing Li, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien