Patents by Inventor Chih-Liang Chen

Chih-Liang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384598
    Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20220384414
    Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: CHENG-YU LIN, PO-HSIANG HUANG, POCHUN WANG, CHIH-LIANG CHEN, FONG-YUAN CHANG
  • Patent number: 11513810
    Abstract: A method of configuring a display device interface (DDI) detects a trigger signal, generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter accordingly. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Chung-Wei Wang, Chih-Chung Lin, You-Liang Chen, Pei-Yu Wang
  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Patent number: 11508659
    Abstract: A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guo-Huei Wu, Shun-Li Chen, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11509293
    Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Jerry Chang-Jui Kao, Tzu-Ying Lin
  • Publication number: 20220367440
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20220367458
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU
  • Publication number: 20220367240
    Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Patent number: 11502177
    Abstract: A high-electron mobility transistor includes a substrate, a GaN channel layer over the substrate, an AlGaN layer over the GaN channel layer, a gate recess in the AlGaN layer, a source region and a drain region on opposite sides of the gate recess, a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively, a p-GaN gate layer in and on the gate recess; and a re-grown AlGaN film on the AlGaN layer, on the GaN source layer and the GaN drain layer, and on interior surface of the gate recess.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20220359493
    Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited
    Inventors: Xin-Yong WANG, Li-Chun TIEN, Chih-Liang CHEN
  • Publication number: 20220360775
    Abstract: A video encoding method includes: during a first period, performing an encoding process upon a first block group of a current frame to generate a first block group bitstream; and during a second period, transmitting a second block group bitstream derived from encoding a second block group of the current frame, wherein the second period overlaps the first period. The encoding process includes: during a first time segment of the first period, performing a first in-loop filtering process upon a first group of pixels; and during a second time segment of the first period, performing a second in-loop filtering process upon a second group of pixels, wherein the second time segment overlaps the first time segment, and a non-zero pixel distance exists between a first edge pixel of the first group of pixels and a second edge pixel of the second group of pixels in a filter direction.
    Type: Application
    Filed: April 21, 2022
    Publication date: November 10, 2022
    Applicant: MEDIATEK INC.
    Inventors: Tung-Hsing Wu, Shih-Yu Chen, Jer-Ming Chang, Chih-Hao Chang, Han-Liang Chou
  • Publication number: 20220359651
    Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Inventors: CHE-YUAN CHANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN
  • Publication number: 20220359392
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern above the first conductive pattern, and a third conductive pattern above the first conductive pattern, all extending along a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 10, 2022
    Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
  • Patent number: 11495687
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 11495497
    Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Ho Che Yu
  • Patent number: 11493977
    Abstract: An electronic device includes a processor, a battery, a charging circuit, a controller, and an arithmetic logic unit. The processor is capable of operating at a preset frequency or a low frequency. The charging circuit is electrically connected to an external power supply and a battery and transmits a disconnection signal and to be powered by the battery when the external power supply and the charging circuit are changed from a connected state to a disconnected state. The controller is configured to transmit a first control signal when the external power supply and the charging circuit are changed from the connected state to the disconnected state. The arithmetic logic unit is configured to transmit a frequency reduction signal to the processor according to the disconnection signal and the first control signal, so that the processor reduces the preset frequency to the low frequency and operates at the low frequency.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: November 8, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chia-Liang Wei, Shiuan-Shuo Shiu, Ssu-Yun Chen, Jei-Hsiang Ma, Yi-Ming Lee, Chih-Wei Chung, Ming-You Jiang, Wei-Hao Lee
  • Patent number: 11489048
    Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11486695
    Abstract: The present invention provides a measurement device for grinding wheel. One or more thickness measurement device is disposed slidably on a platform. A spinning device is disposed on the platform. A grinding wheel is fixed on the spinning device. The spinning shaft spins the grinding wheel. The one or more thickness measurement device measures the flatness condition of the grinding wheel. Furthermore, according to the present invention, a diameter measurement device is disposed inside the platform and measures the roundness of the outer periphery of the grinding wheel. Since the structure can be disassembled easily, the whole measurement device for grinding wheel can be carried conveniently. In addition, measurements can be performed by users on the site where the grinding wheel is located for real-timely understanding the real size and wear condition of grinding wheel.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 1, 2022
    Assignee: Metal Industries Research & Development Centre
    Inventors: Chin-Kang Chen, Ching-An Lin, Chia-Ho Cheng, Sung-Liang Hsieh, Chih-Hsin Chang
  • Publication number: 20220345116
    Abstract: An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.
    Type: Application
    Filed: July 9, 2022
    Publication date: October 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Jerry Chang-Jui KAO, Tzu-Ying LIN