Patents by Inventor Chih-Lung Lee

Chih-Lung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119539
    Abstract: A display, including a supporting layer and a flexible display panel, is provided. The supporting layer has at least two extending sections and at least one bending section, connected therebetween and adapted to be bent along an axis as a rotation axis. The supporting layer has at least one groove at the bending section and at least one indentation at a bottom surface of the groove. An extending direction of the groove is parallel to the axis. An extending direction of the indentation is not parallel to the axis. The supporting layer has a first thickness at each extending section, a second thickness at the groove, and a third thickness at the indentation. The first, second, and third thicknesses are different from one another. The flexible display is disposed on the supporting layer. The groove and the flexible display are respectively located on two opposite sides of the supporting layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: September 14, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chih-Tsung Lee, Zih-Shuo Huang, Kun-Lung Hsieh, Kai-Yu Yu
  • Patent number: 10672880
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 2, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (SheZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
  • Publication number: 20190027506
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Application
    Filed: December 13, 2016
    Publication date: January 24, 2019
    Inventors: PO-LI SHIH, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, WEI-CHIH CHANG, I-MIN LU
  • Patent number: 10062791
    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 28, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Publication number: 20180097116
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Application
    Filed: November 23, 2017
    Publication date: April 5, 2018
    Inventors: HSIN-HUA LIN, YI-CHUN KAO, CHIH-LUNG LEE, PO-LI SHIH, KUO-LUNG FANG
  • Patent number: 9893198
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9893197
    Abstract: A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Kuo-Lung Fang, Po-Li Shih
  • Patent number: 9859440
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 2, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao, Chih-Lung Lee, Po-Li Shih, Kuo-Lung Fang
  • Patent number: 9823528
    Abstract: An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wu-Liu Tsai, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9799680
    Abstract: A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 24, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9741862
    Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 22, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Chih-Lung Lee, Hsin-Hua Lin, Kuo-Lung Fang
  • Patent number: 9576984
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: February 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
  • Patent number: 9576990
    Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: February 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Po-Li Shih
  • Patent number: 9548392
    Abstract: A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 17, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Chih-Lung Lee, Kuo-Lung Fang, Hsin-Hua Lin
  • Publication number: 20160351717
    Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.
    Type: Application
    Filed: July 7, 2015
    Publication date: December 1, 2016
    Inventors: PO-LI SHIH, YI-CHUN KAO, CHIH-LUNG LEE, HSIN-HUA LIN, KUO-LUNG FANG
  • Publication number: 20160351719
    Abstract: A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.
    Type: Application
    Filed: August 25, 2015
    Publication date: December 1, 2016
    Inventors: PO-LI SHIH, YI-CHUN KAO, CHIH-LUNG LEE, KUO-LUNG FANG, HSIN-HUA LIN
  • Publication number: 20160343865
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Application
    Filed: June 30, 2015
    Publication date: November 24, 2016
    Inventors: KUO-LUNG FANG, YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, CHIH-LUNG LEE
  • Publication number: 20160343738
    Abstract: A method for manufacturing a thin film transistor (TFT), the TFT includes a gate, a first insulation layer, a channel layer, a source, a drain, a second insulation, and a flat layer. The gate is formed on a base. The first insulation layer is formed on the base to cover the gate and the base. The channel layer is formed on the first insulation layer corresponding to the gate. The second insulation layer is formed on the base to cover the first insulation layer, the channel layer, the source, and the drain. The flat layer includes a first region and a second region and is formed on the second insulation layer. The first region and the second region respectively have different light transmittance.
    Type: Application
    Filed: August 24, 2015
    Publication date: November 24, 2016
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, KUO-LUNG FANG, PO-LI SHIH
  • Publication number: 20160329362
    Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: KUO-LUNG FANG, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, PO-LI SHIH
  • Patent number: 9472674
    Abstract: A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 18, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee