Abstract: An optical sensing circuit includes a first light sensor, a second light sensor, a third light sensor, a capacitor, and a sampling circuit. The first light sensor, the second light sensor, and the third light sensor are respectively covered by a first color filter, a second color filter, and a third color filter. The first light sensor is coupled to the capacitor, the sampling circuit, and the third light sensor. The second light sensor is coupled to the first light sensor and is configured to receive a first sensing signal. The third light sensor is coupled between the first light sensor and a voltage source.

Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.

Abstract: Techniques and tools are described for decoding jointly coded information. For example, a decoder decodes a variable length code [“VLC”] signaled at macroblock level that jointly represents a transform type signal level, transform type, and subblock pattern. The decoder decodes one or more VLCs signaled at block level, each jointly representing a transform type and subblock pattern. The decoder may select between multiple VLC tables for the VLCs signaled macroblock level and/or block level.

Abstract: The disclosure provides a recycle apparatus. The recycle apparatus is configured to separate a back sheet and a glass sheet assembly of a photovoltaic module. The recycle apparatus includes a conveyor, a flattening device, and a cutting tool. The conveyor includes a first roller and a second roller opposite to each other. The flattening device is located aside the first roller and the second roller. The cutting tool is located aside the flattening device. The flattening device is located between the first roller and the second roller of the conveyor and the cutting tool. The first roller and the second roller is configured to clamp the photovoltaic module and to feed the photovoltaic module to the flattening device configured to flatten the photovoltaic module and to the cutting tool configured to separate the back sheet from the glass sheet assembly.

Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.

Abstract: When encoding/decoding a current block of a current picture using intra block copy (“BC”) prediction, the location of a reference block is constrained so that it can be entirely within an inner search area of the current picture or entirely within an outer search area of the current picture, but cannot overlap both the inner search area and the outer search area. In some hardware-based implementations, on-chip memory buffers sample values of the inner search area, and off-chip memory buffers sample values of the outer search area. By enforcing this constraint on the location of the reference block, an encoder/decoder can avoid memory access operations that are split between on-chip memory and off-chip memory when retrieving the sample values of the reference block. At the same time, a reference block close to the current block may be used for intra BC prediction, helping compression efficiency.

Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.

Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.

Abstract: A video codec uses fractional increments of quantization step size at high bit rates to permit a more continuous variation of quality and/or bit rate as the quantization scale changes. For high bit rate scenarios, the bit stream syntax includes an additional syntax element to specify fractional step increments (e.g., half step) of the normal quantizer scale step sizes.

Abstract: Techniques and tools are described for decoding jointly coded information. For example, a decoder decodes a variable length code [“VLC”] signaled at macroblock level that jointly represents a transform type signal level, transform type, and subblock pattern. The decoder decodes one or more VLCs signaled at block level, each jointly representing a transform type and subblock pattern. The decoder may select between multiple VLC tables for the VLCs signaled macroblock level and/or block level.

Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.

Abstract: A minimally invasive bone fracture positioning device includes a sleeve, a movable unit, and a support. The sleeve includes an alignment portion located on a longitudinal axis of the sleeve. The movable unit includes a positioning portion. The positioning portion is located on the longitudinal axis and is spaced from the alignment portion. The movable unit is mounted in a radial direction of the sleeve. The movable unit is slideable relative to the sleeve along the longitudinal axis. A support is coupled to the sleeve and the movable unit. The movable unit is spaced from the sleeve by the support.

Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.

Abstract: The present disclosure provides an electronic device, and the electronic device includes a plurality of touch sensing electrodes and a plurality of ultrasonic fingerprint sensing electrodes. The plurality of ultrasonic fingerprint sensing electrodes are disposed on the plurality of touch sensing electrodes, and a portion of the plurality of touch sensing electrodes are not overlapped with the plurality of ultrasonic fingerprint sensing electrodes.

Abstract: With adaptive multiple quantization, a video or other digital media codec can adaptively select among multiple quantizers to apply to transform coefficients. The switch in quantizers can be signaled at the sequence level or frame level of the bitstream syntax, or can be implicitly specified in the syntax.

Abstract: A radio frequency (RF) positioning system comprises transceivers, positioning tags, processing units and a computing host. One or multiple positioning tags are attached to a target object being located. When the transceivers first generate and transmit transmission signals, one or multiple tag antennas in the positioning tag receive the transmission signals and transmit back modulated signals. The transceivers then receive and transmit the modulated signals to the processing units. The processing units are configured to obtain received signals, and calculate frequency differences based on the received signals and the transmission signals. The computing host calculates position coordinates of tag antennas based on the frequency differences, and then calculates the orientation of the target object being located according to the position coordinates of the tag antennas.

Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.

Abstract: Techniques for recording video from a bitstream are described. In at least some implementations, video data generated as part of a communication session is recorded. According to various implementations, techniques described herein enable portions of an encoded bitstream of video data to be directly recorded as encoded frames and without requiring re-encoding of decoded frames.

Abstract: Approaches to selection of motion vector (“MV”) precision during video encoding are presented. These approaches can facilitate compression that is effective in terms of rate-distortion performance and/or computational efficiency. For example, a video encoder determines an MV precision for a unit of video from among multiple MV precisions, which include one or more fractional-sample MV precisions and integer-sample MV precision. The video encoder can identify a set of MV values having a fractional-sample MV precision, then select the MV precision for the unit based at least in part on prevalence of MV values (within the set) having a fractional part of zero. Or, the video encoder can perform rate-distortion analysis, where the rate-distortion analysis is biased towards the integer-sample MV precision. Or, the video encoder can collect information about the video and select the MV precision for the unit based at least in part on the collected information.

Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.