Patents by Inventor Chih-Ming Huang

Chih-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9082617
    Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 14, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yuan Su, Hung-Ta Huang, Ping-Hao Lin, Hung-Che Liao, Hung-Yu Chiu, Chao-Hsuan Pan, Wen-Tsung Chen, Chih-Ming Huang
  • Publication number: 20150171069
    Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 18, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yuan SU, Hung-Ta HUANG, Ping-Hao LIN, Hung-Che LIAO, Hung-Yu CHIU, Chao-Hsuan PAN, Wen-Tsung CHEN, Chih-Ming HUANG
  • Publication number: 20150125705
    Abstract: The invention relates to a display rear shell with waterproof and fireproof properties comprising a main layer of a pulp made from hardwood in an amount from 80% to 90% by weight of the main layer, a pulp waterproof composition in an amount from 5% to 15% by weight of the main layer, and a flame retardant in an amount of a remaining weight percentage by weight of the main layer, a fireproof layer and a waterproof layer, in place of a traditional plastic display rear shell using plastic materials for characteristics as waterproof, fireproof and light weight.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicants: SHENYANG TONGFANG MULTIMEDIA TECHNOLOGY CO., LTD., TONGFANG GLOBAL LIMITED
    Inventors: TH LAM, WEN-SHENG LU, CHIH-MING HUANG, TSUNG-HSIEN CHUANG, CHRISTOPHER NG
  • Publication number: 20150124441
    Abstract: A rotary lighting fixture having a speaker with a playback function is revealed herein, comprising a shell having an opening, a speaker fitted inside the shell, and an annular LED module having plural LEDs fitted at the opening of the shell for illumination and playback functions. In addition, the lighting fixture also combines with a power supply base with a rotary function embedded in a ceiling and a wall for substantially saving space in use thereof, promoting interior designs by its aesthetic appearance and adjusting angles of incidence from the LEDs as desired.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicants: SHENYANG TONGFANG MULTIMEDIA TECHNOLOGY CO., LTD., TONGFANG GLOBAL LIMITED
    Inventors: TH LAM, WEN-SHENG LU, CHIH-MING HUANG, TSUNG-HSIEN CHUANG, CHRISTOPHER NG
  • Publication number: 20150102433
    Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.
    Type: Application
    Filed: September 16, 2014
    Publication date: April 16, 2015
    Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
  • Patent number: 8866236
    Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: October 21, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
  • Patent number: 8802507
    Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 12, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
  • Patent number: 8716070
    Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 6, 2014
    Assignee: Siliconware Precision Industries Co. Ltd.
    Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
  • Publication number: 20140080264
    Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 20, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
  • Patent number: 8618641
    Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: December 31, 2013
    Assignee: Siliconware Precision Industries Co., Ltd
    Inventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
  • Patent number: 8564115
    Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: October 22, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Chun-An Huang, Chih-Ming Huang
  • Patent number: 8546183
    Abstract: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 1, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Chih-Ming Huang
  • Patent number: 8420430
    Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
  • Patent number: 8367926
    Abstract: An electronic apparatus includes an enclosure defining a connector port, and a cover mechanism. The cover mechanism includes a bracket mounted to the enclosure, a cover rotatably mounted to the bracket to cover or uncover the connector port. The cover includes an elastic lock. When the cover is rotated to cover the connector port, the elastic lock is engaged with a sidewall of the connector port.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: February 5, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Tang Peng, Chih-Ming Huang
  • Patent number: 8304891
    Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
  • Publication number: 20120241937
    Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.
    Type: Application
    Filed: June 8, 2012
    Publication date: September 27, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Chun-An Huang, Chih-Ming Huang
  • Patent number: 8241059
    Abstract: A connector and printed circuit board assembly includes a printed circuit board, a connector fixed on the printed circuit board, and a fixing board fixed on the connector, the fixing board defining a through hole, a connecting member fixed on the printed circuit board adjacent to the connector, a threaded retainer, and a threaded post securely connected with the connecting member. The threaded post passes through the through hole and seats the threaded retainer to lock the connector onto the printed circuit board.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: August 14, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Wei-Chao Huang, Chih-Ming Huang
  • Patent number: 8198689
    Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: June 12, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Chun-An Huang, Chih-Ming Huang
  • Patent number: 8183092
    Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: May 22, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Chih-Ming Huang, Han-Ping Pu, Yu-Po Wang, Cheng-Hsu Hsiao
  • Patent number: D711383
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: August 19, 2014
    Assignees: Tongfang Global Limited, Shengyang Tongfang Multimedia Technology Co., Ltd.
    Inventors: Th Lam, Wen-Sheng Lu, Chih-Ming Huang, Tsung-Hsien Chuang, Christopher Ng