Patents by Inventor Chih-Ming Huang

Chih-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090057799
    Abstract: A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 5, 2009
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chih-Ming Huang, Chien-Ping Huang, Chin-Huang Chang, Cheng-Hsu Hsiao
  • Publication number: 20090039527
    Abstract: A sensor-type package and a method for fabricating the same are provided. A wafer having a plurality of semiconductor chips is provided, wherein a plurality of holes are formed on a first surface of each of the semiconductor chips, and a plurality of metallic pillars formed in the holes and a plurality of bond pads connected to the metallic pillars form through silicon vias (TSVs). A groove is formed on a second surface of each of the semiconductor chips to expose the metallic pillars. A plurality of sensor chips having TSVs are stacked in the grooves of the semiconductor chips and electrically connected to the exposed metallic pillars. A transparent cover is mounted onto the second surfaces of the semiconductor chips to cover the grooves. A plurality of conductive components are implanted on the bond pads of the semiconductor chips. The wafer is cut along borders among the semiconductor chips.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 12, 2009
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Tse-Wen Chang, Chin-Huang Chang, Chih-Ming Huang
  • Publication number: 20090039488
    Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.
    Type: Application
    Filed: August 11, 2008
    Publication date: February 12, 2009
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
  • Publication number: 20090014860
    Abstract: A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.
    Type: Application
    Filed: January 29, 2008
    Publication date: January 15, 2009
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Lun Liu, Jung-Pin Huang, Chin-Huang Chang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20090004784
    Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
    Type: Application
    Filed: September 4, 2008
    Publication date: January 1, 2009
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chien-Ping Huang, Yu-Po Wang, Chih-Ming Huang
  • Publication number: 20080303111
    Abstract: The invention discloses a sensor package and a method for fabricating the same. The sensor package includes: a substrate with an opening; a sensor chip disposed in the opening and electrically connected to the substrate; an encapsulant filling spacing between the sensor chip and the opening so as to secure the sensor chip to the substrate; and a transparent cover attached to the substrate via an adhesive layer, wherein the adhesive layer covers the sensor chip and bonding wires and is formed with an opening for exposing sensor region of the sensor chip. Securing the sensor chip in the opening of the substrate reduces the height of the sensor package, and meanwhile the process cost is reduced by eliminating the need of formation of conductive bumps on the sensor chip or the transparent cover and eliminating the need of specially designed substrate.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 11, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Tse-Wen Chang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20080296716
    Abstract: A sensor semiconductor device and a manufacturing method thereof are disclosed. The method includes: providing a light-permeable carrier board with a plurality of metallic circuits; electrically connecting the metallic circuits to a plurality of sensor chips through conductive bumps formed on the bond pads of the sensor chips, wherein the sensor chips have been previously subjected to thinning and chip probing; filling a first dielectric layer between the sensor chips to cover the metallic circuits and peripheries of the sensor chips; forming a second dielectric layer on the sensor chips and the first dielectric layer; forming grooves between the sensor chips for exposing the metallic circuits such that a plurality of conductive traces electrically connected to the metallic circuits can be formed on the second dielectric layer; and singulating the sensor chips to form a plurality of sensor semiconductor devices.
    Type: Application
    Filed: May 7, 2008
    Publication date: December 4, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chih-Ming Huang, Cheng-Hsu Hsiao, Chun-Chi Ke
  • Publication number: 20080283982
    Abstract: The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 20, 2008
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Chung-Lun Liu, Chin-Huang Chang, Chien-Ping Huang, Chang-Yueh Chan, Chih-Ming Huang
  • Publication number: 20080283971
    Abstract: A semiconductor device and a fabrication method thereof are disclosed. The method includes attaching a wafer with a plurality of chips on a carrier board having an insulating layer, a plurality of conductive circuits and a bottom board; forming a plurality of first grooves between solder pads of adjacent chips to expose the conductive circuits, and filling the first grooves with an insulating adhesive layer; forming second grooves in the insulating adhesive layer; and cutting among the chips to separate the chips from one another.
    Type: Application
    Filed: April 14, 2008
    Publication date: November 20, 2008
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chien-Ping Huang, Chin-Huang Chang, Chih-Ming Huang
  • Patent number: 7445957
    Abstract: A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: November 4, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Cheng-Hsu Hsiao, Chih-Ming Huang
  • Patent number: 7446307
    Abstract: A sensor semiconductor device and a fabrication method thereof are provided. The fabrication method includes mounting a sensor chip on a surface of a substrate; forming a transparent cover on the sensor chip; forming a dielectric layer and a circuit layer on the substrate, wherein the sensor chip is electrically connected to the substrate through the circuit layer and the transparent cover is exposed from the dielectric layer such that light can pass through the transparent cover to reach a sensor region of the sensor chip and allow the sensor chip to operate; and implanting a plurality of solder balls on another surface of the substrate to electrically connect the sensor chip to an external device. The sensor semiconductor device can be cost-effectively fabricated, and the circuit cracking and known good die (KGD) problems of the prior art can be avoided.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: November 4, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Chih-Ming Huang, Cheng-Yi Chang
  • Publication number: 20080265385
    Abstract: A semiconductor package using copper wires and a wire bonding method for the same are proposed. The package includes a carrier having fingers and a chip mounted on the carrier. The method includes implanting stud bumps on the fingers of the carrier and electrically connecting the chip and the carrier by copper wires with one ends of the copper wires being bonded to bond pads of the chip and the other ends of the copper wires being bonded to the stud bumps on the carrier. The implanted stud bumps on the carrier improve bondability of the copper wires to the carrier and thus prevent stitch lift. With good bonding, residues of copper wires left behind after a bonding process have even tail ends and uniform tail length to enable fabrication of solder balls of uniform size, thereby eliminating a conventional step of implanting stud bumps on the bond pads of chips and preventing ball lift from occurring.
    Type: Application
    Filed: June 27, 2008
    Publication date: October 30, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Han-Lung Tsai, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20080258306
    Abstract: The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 23, 2008
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Cheng-Hsu Hsiao, Cheng-Chia Chiang
  • Publication number: 20080251937
    Abstract: A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 16, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20080246142
    Abstract: A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Jeng-Yuan Lai, Chien-Ping Huang, Chih-Ming Huang, Yu-Po Wang, Cheng-Hsu Hsiao
  • Publication number: 20080237767
    Abstract: A sensor-type semiconductor device and manufacturing method thereof are disclosed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20080230913
    Abstract: The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices.
    Type: Application
    Filed: March 18, 2008
    Publication date: September 25, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Chin-Huang Chang, Chih-Ming Huang, Chun-Chi Ke
  • Patent number: 7423340
    Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: September 9, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien Ping Huang, Yu-Po Wang, Chih-Ming Huang
  • Publication number: 20080197438
    Abstract: This invention discloses a sensor semiconductor device and a manufacturing method thereof, including: providing a wafer having a plurality of sensor chips, forming a plurality of grooves between bond pads on active surfaces of the adjacent sensor chips; forming conductive traces in the grooves for electrically connecting the bond pads; mounting a transparent medium on the wafer for covering sensing areas of the sensor chips; thinning the sensor chips from the non-active surfaces down to the grooves, thereby exposing the conductive traces; cutting the wafer to separate the sensor chips; mounting the sensor chips on a substrate module having a plurality of substrates, electrically connecting the conductive traces to the substrates; providing an insulation material on the substrate module and between the sensor chips so as to encapsulate the sensor chips but expose the transparent medium; and cutting the substrate module to separate a plurality of resultant sensor semiconductor devices.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 21, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chien-Ping Huang, Tse-Wen Chang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20080174030
    Abstract: The present invention provides a multi-chip stacking structure. The multichip stacking structure comprises: a chip carrier; a first and a second chip modules respectively having a plurality of first and a plurality of second chips, wherein each chips has a bond pad and the chips are stacked on the chip carrier in a step-like manner to expose the bond pads; and a plurality of bonding wires for electrically connecting the bond pads of the first and the second chip modules to the chip carrier, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer having fillers therein to support the bottom chip, and the bottom chip is deviated from the top chip horizontally in a direction toward the bonding wires of the first chip module.
    Type: Application
    Filed: January 23, 2008
    Publication date: July 24, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Lun Liu, Chin-Huang Chang, Yi-Feng Chang, Jung-Pin Huang, Chih-Ming Huang