Patents by Inventor Chih-Ming Lai

Chih-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342193
    Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen, Ken-Hsien Hsieh, Chin-Hsiang Lin
  • Publication number: 20220149734
    Abstract: A control circuit of a power converter includes a sensing circuit, a ramp signal generation circuit and a PWM circuit. The sensing circuit, coupled to an output circuit, provides a current sensing signal. The ramp signal generation circuit includes a transient circuit and a signal generation circuit. The transient circuit receives the current sensing signal and generates a variable reference voltage. The signal generation circuit provides a ramp signal according to the variable reference voltage. The PWM circuit provides a PWM signal to the output circuit according to the ramp signal. When current sourcing occurs, it continues for a first default time. A transient state during current sourcing continues for a second default time less than first default time. The variable reference voltage is changed from a default value to an adjusted value during the second default time and restored to the default value after the second default time.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 12, 2022
    Inventors: Chih-Lien CHANG, Wei-Hsiu HUNG, Chun-Ming LU, Min-Rui LAI
  • Patent number: 11322362
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Min Hsiao, Chih-Ming Lai, Chien-Wen Lai, Ya Hui Chang, Ru-Gun Liu
  • Publication number: 20220111917
    Abstract: A modular vehicle body includes a pair of outer frames. An inner board space with a fixed width is defined between the outer frames. Each outer frame includes a front side board and a door sill. The front side board includes a main board provided with a vertical board having a predetermined width. A first flange is provided on a side of the vertical board. The door sill includes an inner board provided with a horizontal board having a predetermined width. A second flange is provided on a side of the horizontal board. The inner board is fixedly coupled to the main board. The first flange and the second flange form an outer edge. A width between the outer edges of the pair of outer frames is set to correspond to a width of a vehicle body.
    Type: Application
    Filed: March 31, 2021
    Publication date: April 14, 2022
    Inventors: CHIA-HONG CHEN, KAI-WEI TSENG, CHIH-MING LAI
  • Publication number: 20220108990
    Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.
    Type: Application
    Filed: December 16, 2021
    Publication date: April 7, 2022
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
  • Patent number: 11294286
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Cheng-I Huang, Chih-Ming Lai, Chien-Wen Lai, Ken-Hsien Hsieh, Shih-Ming Chang, Yuan-Te Hou
  • Patent number: 11245233
    Abstract: The disclosure relates to a cable concentrator and an electronic device having the same, where the cable concentrator includes main body and ground partition plate. The main body includes sidewall portions and bottom plate portion together forming accommodation portion to accommodate cable connectors. The bottom plate portion has positive terminal holes and negative terminal holes. The ground partition plate is located in the accommodation portion and divides the accommodation portion. The ground partition plate has ground bent tabs respectively corresponding to the negative terminal holes of the bottom plate portion and are electrically connected to negative terminals on a circuit board and thus grounding the negative terminals.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 8, 2022
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Chih-Ming Lai, Yung-Shun Kao
  • Patent number: 11222899
    Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
  • Patent number: 11201064
    Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Chih-Min Hsiao, Chien-Wen Lai, Ru-Gun Liu, Chih-Ming Lai, Wei-Shuo Su, Yu-Chen Chang
  • Publication number: 20210373443
    Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Hsu-Ting HUANG, Tung-Chin WU, Shih-Hsiang LO, Chih-Ming LAI, Jue-Chin YU, Ru-Gun LIU, Chin-Hsiang LIN
  • Publication number: 20210366844
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Publication number: 20210366726
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20210351549
    Abstract: The disclosure relates to a cable concentrator and an electronic device having the same, where the cable concentrator includes main body and ground partition plate. The main body includes sidewall portions and bottom plate portion together forming accommodation portion to accommodate cable connectors. The bottom plate portion has positive terminal holes and negative terminal holes. The ground partition plate is located in the accommodation portion and divides the accommodation portion. The ground partition plate has ground bent tabs respectively corresponding to the negative terminal holes of the bottom plate portion and are electrically connected to negative terminals on a circuit board and thus grounding the negative terminals.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 11, 2021
    Applicant: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Chih-Ming LAI, Yung-Shun KAO
  • Patent number: 11171089
    Abstract: A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX-1) having a first metal pattern pitch (MX-1P); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreXP) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20210334446
    Abstract: A device includes a first cell, a second cell, and first isolation portions. The second cell is adjacent the first cell. The first and second cells are arranged in a first direction, and the first cell includes first and second conductive structures. The first conductive structures extend in the first direction. Each of the first conductive structures has a first end facing the second cell. The second conductive structures extend in the first direction. The first and second conductive structures are alternately arranged in a second direction different from the first direction. The first isolation portions are respectively abutting the first ends of the first conductive structures. Two of the first isolation portions are misaligned with each other in the second direction.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 28, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei PENG, Chih-Ming LAI, Jiann-Tyng TZENG
  • Patent number: 11159164
    Abstract: An integrated circuit includes a first and a second active region, a first contact, a second contact and a first insulating layer. The first active region is in a substrate, extends in a first direction, and is located on a first level. The second active region is in the substrate, extends in the first direction, is located on the first level, and is separated from the first active region in a second direction. The first contact is coupled to the first and the second active region, extends in the second direction, is located on a second level, and overlaps the first and the second active region. The second contact extends in the second direction, overlaps the first contact, and is located on a third level. The first insulating layer extends in the second direction, and is between the second contact and the first contact.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20210280455
    Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN
  • Publication number: 20210280607
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20210282286
    Abstract: A casing assembly having at least one configuration for blocking extraneous material and including first shell part and second shell part. First shell part includes contact portion and first recess portion. Second shell part includes step portion and protrusion portion. Step portion is in contact with contact portion of first shell part and forms decorative slot exposed to outside with contact portion. First recess portion is located on side of contact portion that is located away from decorative slot. Protrusion portion is located on side of step portion that is located away from decorative slot and located in first recess portion. Protrusion portion has top surface facing toward first recess portion, first recess portion has bottom surface, and idle cavity is formed between top surface of protrusion portion and bottom surface of first recess portion.
    Type: Application
    Filed: July 2, 2020
    Publication date: September 9, 2021
    Applicant: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Chih-Ming LAI, Yu Chi PENG
  • Publication number: 20210272808
    Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Chih-Min HSIAO, Chien-Wen LAI, Ru-Gun LIU, Chih-Ming LAI, Shih-Ming CHANG, Yung-Sung YEN, Yu-Chen CHANG