Patents by Inventor Chih-Ming Lai

Chih-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142342
    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: November 12, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
  • Publication number: 20240371653
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Min HSIAO, Chih-Ming LAI, Chien-Wen LAI, Ya Hui CHANG, Ru-Gun LIU
  • Publication number: 20240371868
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Publication number: 20240363393
    Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Patent number: 12129242
    Abstract: The present invention provides novel substituted benzimidazole derivatives used as DAAO inhibitors and for treatment and/or prevention of neurological disorders.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: October 29, 2024
    Assignees: NATIONAL TAIWAN UNIVERSITY, NATIONAL YANG MING CHIAO TUNG UNIVERSITY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: Yufeng Jane Tseng, Yu-Li Liu, Chung-Ming Sun, Wen-Sung Lai, Chih-Min Liu, Hai-Gwo Hwu
  • Publication number: 20240356194
    Abstract: A quick-release module for antenna connectors includes first and second double connector assemblies. The first double connector assembly includes a bottom plate and two first connectors extending from the bottom plate. The bottom plate is integrated with the first connectors. Each first connector includes an inclined outer wall inclined away from the bottom plate and a first engaging portion located between the inclined outer wall and the bottom plate. The second double connector assembly is detachably plugged into the first double connector assembly and includes a housing base and two second connectors fixed on the housing base. Each second connector includes a first elastic arm and a second engaging portion located at an end of the first elastic arm. When the second double connector assembly is plugged into the first double connector assembly, the second engaging portion moves along the inclined outer wall and engages with the first engaging portion.
    Type: Application
    Filed: February 20, 2024
    Publication date: October 24, 2024
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Chih-Ming Lai, Yung-Shun Kao, Fang-Cih Chen
  • Patent number: 12125712
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Min Hsiao, Chih-Ming Lai, Chien-Wen Lai, Ya Hui Chang, Ru-Gun Liu
  • Patent number: 12125850
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Patent number: 12123767
    Abstract: A light sensor includes an optoelectronic device and a light guide element. The light guide element has a first light incident surface and a light exit surface, so as to allow an incident light to enter the light guide element from the first light incident surface and then exit to the optoelectronic device from the light exit surface; wherein at least one of the light incident surface and the light exit surface has a single curved surface.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: October 22, 2024
    Assignee: Qisda Corporation
    Inventors: Che-Yi Lai, Chun-Ming Shen, Chin-Kuei Lee, Chih-Chia Chen
  • Patent number: 12113132
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 12101026
    Abstract: A metal-oxide semiconductor field-effect transistor with asymmetric parallel dies and a method of using the same, including an inductor, a load recognition control unit and a metal-oxide semiconductor field-effect transistor having a first die, a second die, and a switch. The first die is larger in size than the second die. The inductor produces a voltage signal when the load changes. The switch is controlled by the load recognition control unit such that different dies are switched on under different load conditions, thereby improving efficiency under light load condition in addition to reducing volume and cost.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: September 24, 2024
    Assignee: POTENS SEMICONDUCTOR CORP.
    Inventors: Wen Nan Huang, Ching Kuo Chen, Chih Ming Yu, Hsiang Chi Meng, Tung Ming Lai
  • Publication number: 20240297042
    Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Min HSIAO, Chien-Wen LAI, Shih-chun HUANG, Yung-Sung YEN, Chih-Ming LAI, Ru-Gun LIU
  • Patent number: 12080588
    Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Patent number: 12062543
    Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Min Hsiao, Chien-Wen Lai, Ru-Gun Liu, Chih-Ming Lai, Shih-Ming Chang, Yung-Sung Yen, Yu-Chen Chang
  • Publication number: 20240220210
    Abstract: A modulo divider and a modulo division operation method for binary data are provided, including: converting a first variant and a second variant to a variant set according to a first mapping table; generating a fifth variant and a sixth variant according to the variant set; generating a seventh variant and an eighth variant according to the variant set; updating the first variant according to one of the fifth variant and the sixth variant and updating the second variant according to the other one of the fifth variant and the sixth variant; updating the third variant according to one of the seventh variant and the eighth variant and updating the fourth variant according to the other one of the seventh variant and the eighth variant; and outputting the third variant as a result of a modulo division operation in response to determining the updating of the third variant being finished.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 4, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Hsiang Yang, Liang-Hsin Lin, Yu-Ling Kang, Yu-Hui Lin, Chih-Ming Lai
  • Publication number: 20240224470
    Abstract: A heat dissipation assembly and an electric device thereof are provided. An expansion card is fixed in the electric device. The heat dissipation assembly includes a heat dissipation unit and a quick release hook. A first guide block is provided on a first side of the heat dissipation unit, and a first positioning component is provided on the first guide block. The quick release hook includes a slide piece, a pressing component and a spring component. The slide piece includes a buckle slot and a first oblong hole. The first positioning component penetrates the first oblong hole and is provided on the first guide block, such that the slide piece is arranged on the first guide block. The spring component is compressed, a second end of the spring component abuts against the first side; and the spring component is released, the buckle slot abuts against a positioning column.
    Type: Application
    Filed: September 27, 2023
    Publication date: July 4, 2024
    Inventor: Chih-Ming Lai
  • Publication number: 20240213707
    Abstract: A connector protection device includes a protective shell top wall, protective shell side walls, and two position-limiting structures. The protective shell top wall covers a connector top surface and includes a slot corresponding to a connector slot. The slot extends along a first direction. The protective shell side walls are connected to each other and to the protective shell top wall and cover the connector side surfaces. The two position-limiting structures are located adjacent to opposite ends of the slot in the first direction. Each of the position-limiting structures is used to limit a relative position of the expansion card and the connector slot in a second direction perpendicular to the first direction. When the expansion card is inserted into the connector slot through the slot, the expansion card is limited by the two position-limiting structures to maintain the relative position with the connector slot in the second direction.
    Type: Application
    Filed: September 22, 2023
    Publication date: June 27, 2024
    Applicant: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Chih-Ming Lai, Yung-Shun Kao
  • Publication number: 20240213034
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on the first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Application
    Filed: March 11, 2024
    Publication date: June 27, 2024
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Chung-Ju Lee, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau
  • Patent number: 12014926
    Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Min Hsiao, Chien-Wen Lai, Shih-Chun Huang, Yung-Sung Yen, Chih-Ming Lai, Ru-Gun Liu
  • Publication number: 20240194682
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 13, 2024
    Applicant: Tiawan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien WU, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai