Patents by Inventor Chih-Nan Wu

Chih-Nan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9985133
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Cherng Jeng, Chih-Nan Wu, Chun-Che Lin, Ting-Chun Wang
  • Patent number: 9941376
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Patent number: 9876114
    Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiu-Ko JangJian, Chih-Nan Wu, Chun Che Lin, Ting-Chun Wang
  • Patent number: 9601535
    Abstract: The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface, a plurality of sensor elements disposed at the front surface of the substrate. Each of the plurality of sensor elements is operable to sense radiation projected towards the back surface of the substrate. The image sensor also includes a high-k dielectric grid disposed over the back surface of the substrate. The high-k dielectric grid has a high-k dielectric trench and sidewalls. The image sensor also includes a color filter and a microlens disposed over the high-k dielectric grid.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jang Jian, Chih-Nan Wu, Chun Che Lin, Yu-Ku Lin
  • Publication number: 20170040456
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Inventors: Shiu-Ko JANGJIAN, Chi-Cherng JENG, Chih-Nan WU, Chun-Che LIN, Ting-Chun WANG
  • Publication number: 20170033222
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Chih-Nan WU, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Publication number: 20160358854
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 8, 2016
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20160322473
    Abstract: Buffer layers on gates and methods of forming such are described. According to a method embodiment, a gate structure is formed. The gate structure includes a gate dielectric over a substrate, a work function tuning layer over the gate dielectric, and a metal-containing material over the work function tuning layer. A buffer layer is formed on the metal-containing material. A dielectric material is formed on the buffer layer. According to a structure embodiment, a gate structure includes a high-k gate dielectric and a metal gate electrode. A buffer layer is on the metal gate electrode. A dielectric cap is on the buffer layer. An inter-layer dielectric is over the substrate and around the gate structure. A top surface of the inter-layer dielectric is co-planar with a top surface of the dielectric cap.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 3, 2016
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20160322471
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Application
    Filed: June 4, 2015
    Publication date: November 3, 2016
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Patent number: 9478660
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Cherng Jeng, Chih-Nan Wu, Chun-Che Lin, Ting-Chun Wang
  • Patent number: 9466494
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng HsuKu
  • Patent number: 9437484
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20160204245
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 14, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shiu-Ko JANGJIAN, Chi-Cherng JENG, Chih-Nan WU, Chun-Che LIN, Ting-Chun WANG
  • Publication number: 20160190305
    Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.
    Type: Application
    Filed: April 15, 2015
    Publication date: June 30, 2016
    Inventors: Shiu-Ko JangJian, Chih-Nan Wu, Chun Che Lin, Ting-Chun Wang
  • Publication number: 20160141179
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Application
    Filed: December 31, 2014
    Publication date: May 19, 2016
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, W.C. HsuKu
  • Publication number: 20160111325
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: April 17, 2015
    Publication date: April 21, 2016
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20150171125
    Abstract: An image sensor device includes a substrate, a photo sensitive element, a first dielectric structure and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The photo sensitive element is formed on the first side of the substrate for receiving incident light transmitted through the substrate. The first dielectric structure is formed on the second side of the substrate. At least one portion of the convex dielectric lens is located in the first dielectric structure. The convex dielectric lens has a convex side oriented toward the incident light and a planer side oriented toward the photo sensitive element.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 18, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Publication number: 20140263956
    Abstract: The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface, a plurality of sensor elements disposed at the front surface of the substrate. Each of the plurality of sensor elements is operable to sense radiation projected towards the back surface of the substrate. The image sensor also includes a high-k dielectric grid disposed over the back surface of the substrate. The high-k dielectric grid has a high-k dielectric trench and sidewalls. The image sensor also includes a color filter and a microlens disposed over the high-k dielectric grid.
    Type: Application
    Filed: June 6, 2013
    Publication date: September 18, 2014
    Inventors: Shiu-Ko Jang Jian, Chih-Nan Wu, Chun Che Lin, Yu-Ku Lin
  • Patent number: 7514880
    Abstract: A lighting apparatus for a projector comprises a control module, a lamp driver and a transient voltage suppression circuit, in which the control module is used for generating a lighting signal, the lamp driver is used for receiving the lighting signal and controlling a lamp according to the lighting signal, and the transient voltage suppression circuit is disposed between the control module and the lamp driver, used for transmitting said lighting signal to the lamp driver and attenuating a high transient voltage generated at the instant the lamp driver lights up the lamp. The present invention is used to lower the high transient voltage through the transient voltage suppression circuit. Whereby, the control module is protected and the stability of the projector is further enhanced.
    Type: Grant
    Filed: December 25, 2005
    Date of Patent: April 7, 2009
    Assignee: Coretronic Corporation
    Inventors: Jain-Chung Huang, Chih-Neng Tseng, Chih-Nan Wu, Ching-Kao Pan
  • Publication number: 20070257778
    Abstract: A projection apparatus includes a first wireless unit receiving signals from a first external wireless remote controller, a second external wireless unit receiving signals from a second wireless remote controller, a signal-processing unit respectively coupled with the first wireless unit and the second wireless unit to receive signals, a CPU coupled with the signal-processing unit to receive processed signals from the signal-processing unit, and a projecting unit coupled with the CPU to perform a projecting function in accordance with the signal transmitted from the CPU.
    Type: Application
    Filed: January 11, 2007
    Publication date: November 8, 2007
    Inventors: Chih-Neng Tseng, Chih-Nan Wu, Po-Liang Chen