Patents by Inventor Chih-Sen Huang

Chih-Sen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865593
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 9, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9859170
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Patent number: 9831133
    Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Chih-Kai Hsu, Li-Wei Feng, Shih-Hung Tsai, Chien-Ting Lin, Jyh-Shyang Jenq, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20170287843
    Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 5, 2017
    Inventors: Jia-Rong Wu, Ying-Cheng Liu, Ching-Wen Hung, Yi-Hui Lee, Chih-Sen Huang
  • Patent number: 9780199
    Abstract: A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Shih-Fang Tzou
  • Publication number: 20170263744
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Publication number: 20170263597
    Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Shih-Fang Tzou, Yi-Wei Chen, Yung-Feng Cheng, Li-Ping Huang, Chun-Hsien Huang, Chia-Wei Huang, Yu-Tse Kuo
  • Patent number: 9721841
    Abstract: An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 1, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Jun-Jie Wang, Yu-Lin Wang, Ching-Wen Hung, En-Chiuan Liou, Chih-Sen Huang
  • Publication number: 20170194212
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first fin-shaped structure and a second fin-shaped structure on the substrate; forming a first epitaxial layer on the first fin-shaped structure and a second epitaxial layer on the second fin-shaped structure; and forming a cap layer on the first epitaxial layer and the second epitaxial layer. Preferably, a distance between the first epitaxial layer and the second epitaxial layer is between twice the thickness of the cap layer and four times the thickness of the cap layer.
    Type: Application
    Filed: January 28, 2016
    Publication date: July 6, 2017
    Inventors: Ching-Wen Hung, Ying-Cheng Liu, Jia-Rong Wu, Yi-Hui Lee, Chih-Sen Huang
  • Patent number: 9698255
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Patent number: 9698047
    Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Shih-Fang Tzou, Yi-Wei Chen, Yung-Feng Cheng, Li-Ping Huang, Chun-Hsien Huang, Chia-Wei Huang, Yu-Tse Kuo
  • Patent number: 9685337
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Chun-Hsien Lin
  • Publication number: 20170162449
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Patent number: 9673100
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chien-Ting Lin, Shih-Fang Tzou, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Patent number: 9660042
    Abstract: A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Publication number: 20170103896
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
    Type: Application
    Filed: August 23, 2016
    Publication date: April 13, 2017
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Chun-Hsien Lin
  • Publication number: 20170098707
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.
    Type: Application
    Filed: November 5, 2015
    Publication date: April 6, 2017
    Inventors: Ching-Wen Hung, Yi-Kuan Wu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9613969
    Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: April 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Patent number: 9607892
    Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Yu-Cheng Tung
  • Publication number: 20170084721
    Abstract: A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Shih-Fang Tzou