Patents by Inventor Chih-Sen Huang

Chih-Sen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9412745
    Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160225662
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Feng-Yi Chang, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Yi-Kuan Wu, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9401358
    Abstract: A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: July 26, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160204103
    Abstract: A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design.
    Type: Application
    Filed: February 2, 2015
    Publication date: July 14, 2016
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9349653
    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Shih-Hung Tsai, Ssu-I Fu, Chih-Sen Huang, Li-Wei Feng, Jyh-Shyang Jenq
  • Patent number: 9349639
    Abstract: A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang
  • Publication number: 20160141207
    Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 19, 2016
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Patent number: 9331171
    Abstract: The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9324610
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.
    Type: Grant
    Filed: August 10, 2014
    Date of Patent: April 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
  • Publication number: 20160104646
    Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 14, 2016
    Inventors: Ching-Wen Hung, Tsung-Hung Chang, Jia-Rong Wu, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160104647
    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.
    Type: Application
    Filed: November 12, 2014
    Publication date: April 14, 2016
    Inventors: Chao-Hung Lin, Shih-Hung Tsai, Ssu-I Fu, Chih-Sen Huang, Li-Wei Feng, Jyh-Shyang Jenq
  • Publication number: 20160104637
    Abstract: A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Inventors: Ching-Wen Hung, Chih-Sen Huang
  • Publication number: 20160104645
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.
    Type: Application
    Filed: November 10, 2014
    Publication date: April 14, 2016
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chien-Ting Lin, Shih-Fang Tzou, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Publication number: 20160104612
    Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 14, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YI-HUI LEE, TSUNG-HUNG CHANG, CHING-WEN HUNG, JIA-RONG WU, CHING-LING LIN, CHIH-SEN HUANG, YI-WEI CHEN, CHIA-CHANG HSU, SHU-MIN HUANG, HSIN-FU HUANG
  • Patent number: 9312356
    Abstract: The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Yi-Wen Chen
  • Patent number: 9312121
    Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Hui Lee, Tsung-Hung Chang, Ching-Wen Hung, Jia-Rong Wu, Ching-Ling Lin, Chih-Sen Huang, Yi-Wei Chen, Chia-Chang Hsu, Shu-Min Huang, Hsin-Fu Huang
  • Patent number: 9306032
    Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Po-Chao Tsao, Ching-Wen Hung, Jia-Rong Wu, Chien-Ting Lin
  • Publication number: 20160071800
    Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.
    Type: Application
    Filed: October 14, 2014
    Publication date: March 10, 2016
    Inventors: Ching-Wen Hung, Tsung-Hung Chang, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen, Chia Chang Hsu, Hsin-Fu Huang, Chun-Yuan Wu, Shih-Fang Tzou
  • Patent number: 9281367
    Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Patent number: 9281199
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: March 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Shih-Fang Tzou