Abstract: Manufacture of a ferroelectric random-access memory device includes forming a first electrode and an intermetal dielectric (IMD) layer over the first electrode. The IMD layer has a first surface on a first side of the IMD layer distal from the first electrode and a second surface on a second side of the IMD layer proximate to the first electrode. A via is created through the IMD layer, which is aligned with the first electrode underneath and has a side wall extending from the first surface of the IMD layer to the second surface of the IMD layer. A ferroelectric layer is deposited over the IMD layer. The ferroelectric layer includes a first part within the via and a second part extending laterally out from the via over the first surface of the IMD layer, the second part thereafter being removed by chemical mechanical polishing.

Abstract: A compound control circuit comprises an input end, a light-load signal processing circuit, a slow response circuit and a fast response circuit. The compound control circuit is mainly used as an additional circuit of a work control chip, so that although the work control chip only has a single overcurrent protection level, a compound function control of fast and slow speed, high and low level current protection and light-load signal stabilization can be generated through the compound control circuit, so as to meet the complex application environment and compatible requirements of the current power supply.

Abstract: An optical element including a first substrate, a second substrate, a first optical film, a second optical film, and a spacer is provided. The first optical film is disposed on the first substrate and has a first surface and a plurality of first optical microstructures. The first optical microstructures are disposed on the first surface. The second optical film is disposed on the second substrate and has a second surface and a plurality of second optical microstructures. The second surface is opposite to the first surface. The second optical microstructures are disposed on the second surface. The orthogonal projection of the first optical microstructures on the first substrate does not overlap with the orthogonal projection of the second optical microstructures on the first substrate. The spacer is disposed between the first substrate and the second substrate. A wafer level optical module adopting the optical element is also provided.

Abstract: The invention provides an output structure for a power supply, comprising a working circuit board, an output circuit board, a plurality of output connectors, a plurality of heat dissipation plates and a plurality of thermistors. The output circuit board is electrically connected with the working circuit board and is provided with at least one temperature sensing circuit, the plurality of output connectors is arranged on the output circuit board, the plurality of heat dissipation plates is arranged on the output circuit board and close to the output connectors, the plurality of heat dissipation plates senses heat of the output circuit board and at least one of the output connectors at the same time, the plurality of thermistors is arranged corresponding to the plurality of heat dissipation plates one to one and is connected with the at least one temperature sensing circuit.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

Abstract: A diffractive optical element and method for fabricating the diffractive optical element are provided. The diffractive optical element includes a substrate, a first diffractive structure layer and a second diffractive structure layer. The substrate has a first surface and a second surface opposite to the first surface. The first diffractive structure layer is disposed on the first surface of the substrate. The second diffractive structure layer is disposed on the second surface of the substrate. In the method for fabricating the diffractive optical element, at first, the substrate is provided. Then, a first glue material layer/first semiconductor layer is formed and patterned on the first surface of the substrate. Thereafter, a second glue material layer/second semiconductor layer is formed and patterned on the second surface of the substrate.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: The invention provides an output structure for a power supply, comprising a working circuit board, an output circuit board, a plurality of output connectors, a plurality of heat dissipation plates and a plurality of thermistors. The output circuit board is electrically connected with the working circuit board and is provided with at least one temperature sensing circuit, the plurality of output connectors is arranged on the output circuit board, the plurality of heat dissipation plates is arranged on the output circuit board and close to the output connectors, the plurality of heat dissipation plates senses heat of the output circuit board and at least one of the output connectors at the same time, the plurality of thermistors is arranged corresponding to the plurality of heat dissipation plates one to one and is connected with the at least one temperature sensing circuit.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Abstract: An optical element including a substrate, a first optical film and a second optical film. The first optical film and the second optical film are disposed on at least one side of the substrate and are both formed on the substrate. The first optical film has a first surface facing away from the substrate and a plurality of first optical microstructures disposed on the first surface. The second optical film has a second surface facing away from the substrate and a plurality of second optical microstructures disposed on the second surface. The orthogonal projection of the first optical microstructures on the substrate does not overlap the orthogonal projection of the second optical microstructures on the substrate. A wafer level optical module adopting the optical element is also provided.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Abstract: The optical component includes a first substrate, a first diffractive layer formed on the first substrate, a second substrate, a second diffractive layer formed on the second substrate, and a bonding material disposed between the first substrate and the second substrate and connecting the first substrate and the second substrate. The second diffractive layer is disposed opposite to the first diffractive layer, and both the first diffractive layer and the second diffractive layer are located between the first substrate and the second substrate. A gap is formed between the first diffractive layer and the second diffractive layer.