Patents by Inventor Chih-Tsung Lee

Chih-Tsung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200144063
    Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.
    Type: Application
    Filed: December 30, 2019
    Publication date: May 7, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Ling LEE, Shing-Chyang PAN, Keng-Chu LIN, Wen-Cheng YANG, Chih-Tsung LEE, Victor Y. LU
  • Publication number: 20200144975
    Abstract: The present invention provides a receiver including a first band group, a second band group and a mixer. The first band group includes at least one LNA, wherein the first band group is configured to select one first LNA to receive a first input signal to generate an amplified first input signal. The second band group includes at least one LNA, wherein the second band group is configured to select one second LNA to receive a second input signal to generate an amplified second input signal. The first band group and the second band group are coupled to a first input terminal and a second input terminal of the mixer, respectively, and the mixer receives one of the amplified first input signal and the amplified second input signal to generate an output signal.
    Type: Application
    Filed: October 8, 2019
    Publication date: May 7, 2020
    Inventors: Chih-Hao Sun, Yu-Tsung Lo, Yi-Bin Lee
  • Publication number: 20200133127
    Abstract: A method of generating a layout pattern includes disposing a photoresist layer of a resist material on a substrate and disposing a top layer over of the photoresist layer. The top layer is transparent for extreme ultraviolet (EUV) radiation and the top layer is opaque for deep ultraviolet (DUV) radiation. The method further includes irradiating the photoresist layer with radiation generated from an EUV radiation source. The radiation passes through the top layer to expose the photoresist layer.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Tsung SHIH, Chen-Ming WANG, Yahru CHENG, Bo-Tsun LIU, Tsung Chuan LEE
  • Publication number: 20200133141
    Abstract: A method includes reducing refractive index of an environment at or adjacent an extreme ultraviolet (EUV) mask to below 1.0. The EUV mask is in an EUV lithography system that forms a projection beam of EUV radiation using EUV radiation emitted from a radiation source. The method further includes exposing the EUV mask to the projection beam of EUV radiation.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Tsung SHIH, Tsung-Chih CHIEN, Tsung Chuan LEE
  • Publication number: 20200073225
    Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.
    Type: Application
    Filed: August 2, 2019
    Publication date: March 5, 2020
    Inventors: Chih-Tsung SHIH, Tsung-Chih CHIEN, Shih-Chi FU, Chi-Hua FU, Kuotang CHENG, Bo-Tsun LIU, Tsung Chuan LEE
  • Publication number: 20200057383
    Abstract: An extreme ultraviolet (EUV) lithography system includes an extreme ultraviolet (EUV) radiation source to emit EUV radiation, a collector for collecting the EUV radiation and focusing the EUV radiation, a reticle stage for supporting a reticle including a pellicle for exposure to the EUV radiation, and at least one sensor configured to detect particles generated due to breakage of the pellicle.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Inventors: Chih-Tsung SHIH, Bo-Tsun LIU, Tsung Chuan LEE
  • Patent number: 10520803
    Abstract: A projector device includes an illumination module and an imaging module. The imaging module is connected to the illumination module and includes a housing, a relay optical system, and a projection optical system. The housing has a first annular receiving groove and a second annular receiving groove. The first annular receiving groove is closer to the illumination module than the second annular receiving groove. A center axis line of the first annular receiving groove and a center axis line of the second annular receiving groove are on the same axis line. The relay optical system includes a lens received in the first annular receiving groove. The projection optical system includes a lens and a reflecting mirror received in the second annular receiving groove. Mirror centers of the lenses and a mirror center the reflecting mirror are located on the same axis line.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 31, 2019
    Assignee: ARIMA COMMUNICATIONS CORP.
    Inventors: Wen-Tsung Lee, Chih-Huang Wang, Hsiang-Lin Yu, Chao-Cheng Chou, Dung-Rur Juang, Ming-Chao Wu
  • Patent number: 10522360
    Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Ling Lee, Shing-Chyang Pan, Keng-Chu Lin, Wen-Cheng Yang, Chih-Tsung Lee, Victor Y. Lu
  • Publication number: 20190358723
    Abstract: An automatic wire arranging device includes a controller, at least one driving device electrically connected with the controller, a first wire clamping jig connected with the at least one driving device, a second wire clamping jig disposed to the first wire clamping jig, at least one charge-coupled device camera connected with the controller, and at least one puncher pin connected with the at least one driving device. The first wire clamping jig opens a plurality of first clamping slots. Each of the plurality of the first clamping slots opens a through-hole. The second wire clamping jig opens a plurality of second clamping slots. The at least one puncher pin is capable of penetrating through the through-hole and pushing against a core wire to be away from one of the plurality of the first clamping slots and be blocked in one of the plurality of the second clamping slots.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Inventors: Peng Yuan Lee, Jun Long Wu, Ming Tsung Lee, Chih Hau Sun
  • Publication number: 20190337116
    Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Shih-Chi LIN, Kun-Tai WU, You-Hua CHOU, Chih-Tsung LEE, Min Hao HONG, Chih-Jen WU, Chen-Ming HUANG, Soon-Kang HUANG, Chin-Hsiang CHANG, Chih-Yuan YANG
  • Patent number: 10468493
    Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
  • Publication number: 20190331999
    Abstract: A projector device includes an illumination module and an imaging module. The imaging module is connected to the illumination module and includes a housing, a relay optical system, and a projection optical system. The housing has a first annular receiving groove and a second annular receiving groove. The first annular receiving groove is closer to the illumination module than the second annular receiving groove. A center axis line of the first annular receiving groove and a center axis line of the second annular receiving groove are on the same axis line. The relay optical system includes a lens received in the first annular receiving groove. The projection optical system includes a lens and a reflecting mirror received in the second annular receiving groove. Mirror centers of the lenses and a mirror center the reflecting mirror are located on the same axis line.
    Type: Application
    Filed: October 16, 2018
    Publication date: October 31, 2019
    Inventors: WEN-TSUNG LEE, CHIH-HUANG WANG, HSIANG-LIN YU, CHAO-CHENG CHOU, DUNG-RUR JUANG, MING-CHAO WU
  • Publication number: 20190295849
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Patent number: 10388749
    Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang, Chun-Ting Chiang, Chih-Wei Lin, Bo-Yu Su, Chi-Ju Lee
  • Patent number: 10366896
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Patent number: 10357867
    Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
  • Patent number: 10299678
    Abstract: An apparatus for detecting conductance parameter of high protein body fluid sample is provided. The apparatus includes at least one liquid collection element, and at least two electrodes horizontally aligned in the liquid collection element. Also provided are methods for detecting dehydration in a subject, comprising the steps of measuring the conductance parameter of the saliva of the subject.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 28, 2019
    Assignees: CHANG GUNG MEMORIAL HOSPITAL, CHIAYI, NATIONAL APPLIED RESEARCH LABORATORIES, NATIONAL TAIWAN UNIVERSITY
    Inventors: Jen-Tsung Yang, Leng-Chieh Lin, I-Neng Lee, Jo-Wen Huang, Jer-Liang Andrew Yeh, Ming-Yu Lin, Yen-Pei Lu, Chih-Ting Lin, Chia-Hong Gao
  • Patent number: 10269573
    Abstract: A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kun-Mo Lin, Keith Kuang-Kuo Koai, Chih-Tsung Lee, Victor Y. Lu, Yi-Hung Lin
  • Patent number: 10269560
    Abstract: A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic layer deposition (ALD) upon a semiconductor substrate and an associated atomic layer deposition (ALD) method are also disclosed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Tzu Chiu, Hsueh-Hui Kuo, Lin-Jung Wu, Chih-Tsung Lee
  • Patent number: 10190209
    Abstract: A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-En Kao, Ming-Chin Tsai, You-Hua Chou, Chen-Chia Chiang, Chih-Tsung Lee, Ming-Shiou Kuo