Patents by Inventor Chih-Wei Huang

Chih-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220022339
    Abstract: A heat dissipation device is provided and includes: a temperature equalizing plate unit; at least one first vapor chamber unit and at least one second vapor chamber unit disposed on an outer surface of the temperature equalizing plate unit; at least one first tower fin set disposed on the outer surface of the temperature equalizing plate unit to sleeve the first and second vapor chamber units and partially expose the second vapor chamber unit; and at least one second tower fin set disposed on a part of a surface of the first tower fin set to sleeve the exposed part of the second vapor chamber unit.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 20, 2022
    Inventors: Chih-Wei Chen, Cheng-Ju Chang, Jyun-Wei Huang
  • Publication number: 20220018610
    Abstract: A vapor chamber structure including a main vapor chamber, at least one heat dissipation structure, and a plurality of metal blocks is provided. The main vapor chamber includes an upper plate and a lower plate. The main vapor chamber further includes a first cavity formed between the upper plate and the lower plate. The heat dissipation structure is located on an outer surface of the upper plate and fluidly connected to the first cavity of the main vapor chamber. The metal blocks are disposed in the first cavity.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 20, 2022
    Inventors: Chih-Wei CHEN, Cheng-Ju CHANG, Jyun-Wei HUANG
  • Publication number: 20220018609
    Abstract: A three-dimensional heat dissipating device includes a vapor chamber, a heat pipe and a working fluid. The vapor chamber includes an inner cavity, a first capillary structure disposed within the inner cavity, and a first joint connected with the inner cavity. The heat pipe includes a pipe body, a second capillary structure, and a second joint disposed at the pipe body and connected to the first joint, such that a pipe space of the pipe body is in communication with the inner cavity. The second capillary structure includes a first section and a second section. The first section is fixedly disposed within a pipe space and connected to the second section. The second section is curvedly extended from one end of the first section, and connected to the first capillary structure. The working fluid is filled within the pipe space and the inner cavity.
    Type: Application
    Filed: June 28, 2021
    Publication date: January 20, 2022
    Inventors: Chih-Wei Chen, Tien-Yao Chang, Che-Wei Kuo, Hsiang-Chih Chuang, Jyun-Wei Huang, Cheng-Ju Chang
  • Publication number: 20220017780
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: January 20, 2022
    Inventors: JI CUI, CHI-JEN LIU, CHIH-CHIEH CHANG, KAO-FENG LIAO, PENG-CHUNG JANGJIAN, CHUN-WEI HSU, TING-HSUN CHANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUI-CHI HUANG
  • Publication number: 20220018611
    Abstract: A heat dissipation device is provided and includes a vapor chamber unit, a heat pipe set provided on an outer surface of the vapor chamber unit, a first fin set provided on the outer surface of the vapor chamber unit and sleeving the heat pipe set, and a second fin set stacked on the first fin set and sleeving the heat pipe set, where the fin arrangement direction of the first fin set is different from the fin arrangement direction of the second fin set.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 20, 2022
    Inventors: Chih-Wei Chen, Cheng-Ju Chang, Jyun-Wei Huang
  • Publication number: 20220018608
    Abstract: A three-dimensional heat dissipating device includes a vapor chamber, a heat pipe, a working fluid and a solder bonding portion. The vapor chamber includes an inner cavity and a first joint. The first joint is formed with a passage being in communication with the inner cavity. The heat pipe is provided with a pipe space and a second joint. The pipe space is in communication with the inner cavity through the passage. The second joint is sleeved to surround the first joint such that one end surface of the second joint is directly contacted with one surface of the vapor chamber. The working fluid is filled within the pipe space and the inner cavity. The solder bonding portion connected to the second joint and the surface of the vapor chamber for integrating the heat pipe and the vapor chamber together.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 20, 2022
    Inventors: Chih-Wei CHEN, Tien-Yao CHANG, Che-Wei KUO, Hsiang-Chih CHUANG, Jyun-Wei HUANG, Cheng-Ju CHANG
  • Patent number: 11227865
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device can be a recessed access device (RAD) transistor, which includes a substrate, a word line disposed in the substrate and surrounded by a dielectric liner, an isolation layer disposed in the substrate to cap the word line, and an insulative plug penetrating through the isolation layer and extending into the word line.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: January 18, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Publication number: 20220013458
    Abstract: The present disclosure relates to an electrical fuse (e-fuse) device and a method for forming the electrical fuse device. The vertical e-fuse device includes a fuse link disposed over a semiconductor base. A material of the fuse link and a material of the semiconductor base are the same. The vertical e-fuse device also includes a first bottom anode/cathode region and a second bottom anode/cathode region disposed over the semiconductor base. A bottom portion of the fuse link is sandwiched between the first bottom anode/cathode region and the second anode/cathode region. The vertical e-fuse device further includes a top anode/cathode region disposed over the fuse link.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 13, 2022
    Inventor: Chih-Wei HUANG
  • Publication number: 20220013492
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Sung-Hui Huang, Shang-Yun Hou, Ying-Ching Shih, Cheng-Chieh Li
  • Patent number: 11222818
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
  • Publication number: 20220005754
    Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 6, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ren-Shin CHENG, Shih-Hsien WU, Yu-Wei HUANG, Chih Ming SHEN, Yi-Chieh TSAI
  • Patent number: 11213884
    Abstract: A vacuum valve includes first and second blocks. The first block includes a base portion and a frustoconical guiding portion connected to the base portion and tapering away from the base portion to form a shoulder, and defines a discharging channel extending in the base portion and through the guiding portion, in spatial communication with ambient surroundings, and adapted to permit air to flow therethrough and into the ambient surroundings. The second block has an end surface cooperating with the shoulder to define an opening communicated spatially with the ambient surroundings, and an inner surface connected to the end surface and cooperating with the frustoconical guiding portion to define a spiral fluid channel therebetween. The spiral fluid channel is in spatial communication with the discharging channel and the opening, and is for introducing air into the discharging channel via the opening.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 4, 2022
    Assignee: METAL INDUSTRIES RESEARCH AND DEVELOPMENT CENTRE
    Inventors: Nai-Kuang Tang, Chih-Wei Lu, Wan-Yun Huang, Chien-Li Lai
  • Patent number: 11217524
    Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
  • Patent number: 11216049
    Abstract: A bus system is provided. The bus system includes a master device and a plurality of slave devices electrically connected to the master device. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When the alert handshake control line is at a first voltage level and a first slave device want to communicate with the master device, the first slave device controls the alert handshake control line to a second voltage level via the alert handshake pin, such that the slave devices enter a synchronization stage. Among phases of each assignment period, in a first phase corresponding to the first slave device, the first slave device controls the alert handshake control line to the second voltage level via the alert handshake pin.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: January 4, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Huang, Chun-Wei Chiu, Hao-Yang Chang
  • Patent number: 11217555
    Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11218721
    Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: January 4, 2022
    Assignee: MEDIATEK INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20210407908
    Abstract: The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Inventor: Chih-Wei HUANG
  • Publication number: 20210407947
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Publication number: 20210407858
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG, Min CAO, Jung-Hung CHANG, Lo-Heng CHANG, Pei-Hsun WANG, Kuo-Cheng CHIANG
  • Patent number: D940781
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 11, 2022
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Cheng-Wei Huang, Ten-Long Dan, Chun-Wen Chen, Chih-Wei Chuang, Tsui-Wei Lin, Ting-Wei Ku, Chung-Chuan Chu, Chih-Wei Kao