Abstract: A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.

Abstract: A subband synthesis filtering apparatus for M sets of signals is provided. Each set of signals includes N subband sample signals. The apparatus includes a processor for processing the ith set of signals among the M sets of signals, wherein i is an integer index ranging from 0 to (M?1). The processor includes a DCT converting module and a generating module. The DCT converting module converts the N subband sample signals of the ith set of signals into N converted vectors. If i is an odd number, the (2j?1)th subband sample signal among the N subband sample signals is multiplied by negative one in the converting module, wherein j is an integer index ranging from 1 to (N/2). The generating module generates N pulse code modulation signals based on the N converted vectors.

Abstract: A method for eliminating internal reflection signal in a range finding system is disclosed, including the steps of receiving a range-finding signal reflected by an object and an internal reflection signal caused by internal reflection of the range finding system, converting the range finding signal and internal reflection signal, as a combination, into an electrical current signal, cropping the electrical current signal in a time interval for the electrical current signal to pass so as to generate a first electrical signal indicating the internal reflection signal, and subtracting the first electrical signal from the current signal to provide a second electrical signal representing the range-finding signal reflected by the object.

Abstract: A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row. The intersections of the dummy bit line with the first select gate line, the word lines, and the second select gate line are corresponding to a dummy memory cell row. A source line is disposed on the substrate at one side of the memory cell rows, wherein the dummy memory cell row and the dummy bit line are served as a current path for connecting the source line.

Abstract: A synthesis subband filter apparatus is provided. The apparatus is used for processing 18 sets of signals which each includes 32 subband sampling signals in accordance with a specification providing 512 window coefficients. The apparatus includes a processor for processing the 18 sets of signals in sequence. The processor further includes a converting module and a generating module. The converting module is used for converting the 32 subband sampling signals of the set of signals being processed into 32 converted vectors by use of 32-points discrete cosine transform (DCT), and writing the 32 converted vectors into 512 default vectors with a first-in, first-out queue. The generating module is used for generating 32 pulse code modulation (PCM) signals, relative to the set of signals being processed according to a set of synthesis formulae proposed in this invention.

Abstract: A remote-controlled sight of a firearm has an aiming unit and a remote-controlled unit. The aiming unit is detachably disposed on a firearm body of the firearm and the remote-controlled unit connects to the firearm body. The remote-controlled unit has a button, a wireless transmitting module and a wireless receiving module, the wireless transmitting module is electrically connected to the button and the wireless receiving module is electrically connected to the aiming unit. When the button is pressed, a signal is transmitted from the wireless transmitting module and received by the wireless receiving module to actuate the aiming unit.

Abstract: A manufacturing method of a multi-level non-volatile memory includes following steps. First, a tunneling dielectric layer and a charge storage layer are sequentially formed on the substrate. At least two stacked layers are formed on the charge storage layer. Every two stacked layers include an inter-gate dielectric layer, a control gate, and a cap layer in sequence. Next, the charge storage layer between the two stacked layers is removed to form a first trench. After spacers are formed at the sidewalls of the two stacked layers and of the first trench, the charge storage layer outside the two stacked layers is removed. Thereafter, a dielectric layer is formed on the substrate. An assist gate is formed between the two stacked layers and a select gate is respectively formed on the sidewalls outside the two stacked layers. A doped region is then formed in the substrate outside the two stacked layers.

Abstract: A method for programming non-volatile memory utilizes substrate hot carrier effect to conduct programming operations. A forward bias voltage is applied between an N-type well region and a P-type well region so as to inject electrons in the N-type well region into the P-type well region. After that, the electrons are accelerated by a depletion region established by a voltage applied to a source region and a drain region, and a vertical electrical field established between a control gate and the P-type well region further forces the electrons to be injected into a charge storage layer. Since the present invention adopts the substrate hot carrier effect to inject carriers into the charge storage layer, the required program operation voltage is low, which benefits to save power consumption and enhance the reliability of the device.

Abstract: A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.

Abstract: A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-?2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

Abstract: An apparatus for displaying an encoded image is disclosed. The apparatus comprises a display device and a decoding unit. The decoding unit acquires a Bit-Per-Pixel (BPP) value from an encoded image, acquires a bit stream from the encoded image, acquires multiple pixel data indices by segmenting the bit stream every lengths of the BPP value, acquires a pixel color value of each pixel data index by retrieving a palette comprising multiple unique pixel color values respectively labeled by the pixel data indices, and outputs the acquired pixel color values to the display device for display of the encoded image.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.

Abstract: A method for eliminating internal reflection signal in a range finding system is disclosed, including the steps of receiving a range-finding signal reflected by an object and an internal reflection signal caused by internal reflection of the range finding system, converting the range finding signal and internal reflection signal, as a combination, into an electrical current signal, cropping the electrical current signal in a time interval for the electrical current signal to pass so as to generate a first electrical signal indicating the internal reflection signal, and subtracting the first electrical signal from the current signal to provide a second electrical signal representing the range-finding signal reflected by the object.

Abstract: A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.

Abstract: A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

Abstract: A remote-controlled sight of a firearm has an aiming unit and a remote-controlled unit. The aiming unit is detachably disposed on a firearm body of the firearm and the remote-controlled unit connects to the firearm body. The remote-controlled unit has a button, a wireless transmitting module and a wireless receiving module, the wireless transmitting module is electrically connected to the button and the wireless receiving module is electrically connected to the aiming unit. When the button is pressed, a signal is transmitted from the wireless transmitting module and received by the wireless receiving module to actuate the aiming unit.

Abstract: A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of the second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and the adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is disposed between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are disposed under the first stacked gate structure, and the source/drain regions are in the exposed substrate.

Abstract: A subband synthesis filtering apparatus for M sets of signals is provided. Each set of signals includes N subband sample signals. The apparatus includes a processor for processing the ith set of signals among the M sets of signals, wherein i is an integer index ranging from 0 to (M?1). The processor includes a DCT converting module and a generating module. The DCT converting module converts the N subband sample signals of the ith set of signals into N converted vectors. If i is an odd number, the (2j?1)th subband sample signal among the N subband sample signals is multiplied by negative one in the converting module, whereinj is an integer index ranging from 1 to (N/2). The generating module generates N pulse code modulation signals based on the N converted vectors.