Patents by Inventor Chih-Wei Yang
Chih-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250048424Abstract: A channel selecting method includes configuring a main access point to provide a first coverage area in a wireless communication network and performing a channel scanning on a plurality of communication channels to obtain a first area information; assigning an initial preference score to each of the communication channels and adjusting the initial preference score to a first preference score according to the first area information; transmitting a beacon request message to a communication device located in the first coverage area and having a second coverage area; controlling the communication device to perform another channel scanning on the communication channels to obtain a second area information; adjusting the first preference score of each of the communication channels to a second preference score according to the second area information; selecting the communication channel corresponding to the second preference score with a maximum value as a target channel.Type: ApplicationFiled: March 6, 2024Publication date: February 6, 2025Inventors: Chih-Wei CHUNG, Chia-Yi LIEN, Yi-Ju YANG
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Patent number: 12218130Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: GrantFiled: December 1, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Patent number: 12218214Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.Type: GrantFiled: April 15, 2021Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 12219123Abstract: A method for rendering data of a three-dimensional image adapted to an eye position and a display system are provided. The method is used to render the three-dimensional image to be displayed in a three-dimensional space. In the method, a three-dimensional image data used to describe the three-dimensional image is obtained. The eye position of a user is detected. The ray-tracing information between the eye position and each lens unit of a multi-optical element module forms a region of visibility (RoV) that may cover a portion of the three-dimensional image in the three-dimensional space. When coordinating the physical characteristics of a display panel and the multi-optical element module, a plurality of elemental images can be obtained. The elemental images form an integral image that records the three-dimensional image data adapted to the eye position, and the integral image is used to reconstruct the three-dimensional image.Type: GrantFiled: July 8, 2021Date of Patent: February 4, 2025Assignee: LIXEL INC.Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang, Hsin-You Hou, Chih-Wei Shih, Wei-An Chen, Kuan-Yu Chen
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Patent number: 12219747Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.Type: GrantFiled: August 12, 2021Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
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Patent number: 12211921Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.Type: GrantFiled: January 14, 2022Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12204163Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: February 5, 2024Date of Patent: January 21, 2025Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 12185494Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.Type: GrantFiled: November 7, 2022Date of Patent: December 31, 2024Assignee: Delta Electronics, Inc.Inventors: Chin-Ting Chen, Chih-Wei Yang, Shu-Cheng Yang, Che-Wei Chang, Wen-Cheng Huang, Chin-Hung Lee, Chih-Wei Chan
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Publication number: 20240282929Abstract: Provided in the embodiments of the present invention is an anode active substance for secondary batteries, which substance comprises a composite material. The composite material includes silicon particles, a ceramic material formed on at least some areas of the surface of the silicon particles, and a conductive carbon composite material formed on the ceramic material to cover the silicon particles and the ceramic material. In addition, further provided herein are a method for preparing an anode active substance and a lithium secondary battery prepared on the basis of the anode active substance.Type: ApplicationFiled: May 26, 2022Publication date: August 22, 2024Applicant: SINO APPLIED TECHNOLOGY TAIWAN CO., LTD.Inventor: Chih-Wei YANG
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Publication number: 20240243124Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.Type: ApplicationFiled: February 15, 2023Publication date: July 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Yang, Shih-Min Lu, Chi-Sheng Tseng, Yao-Jhan Wang, Chun-Hsien Lin
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Publication number: 20240204085Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.Type: ApplicationFiled: February 3, 2023Publication date: June 20, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Yang, Ssu-I Fu, Chih-Kai Hsu, Chun-Hsien Lin
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Patent number: 11950670Abstract: A waterproof container is adapted for an electronic device with a touch screen. The waterproof container includes an upper component and a lower component. The upper component includes a first layer, a second layer and a third layer. The second layer is disposed between the first layer and the third layer. A second touched part of the second layer is connected to a first touched part of the first layer by a plurality of first connections. The second touched part of the second layer is connected to a third touched part of the third layer by a plurality of second connections, and the plurality of first connections and the plurality of second connections are staggered relative to each other. The lower component is connected to the upper component. An accommodating space is enclosed by the lower component and the upper component for accommodating the electronic device.Type: GrantFiled: December 27, 2021Date of Patent: April 9, 2024Assignee: Universal Trim Supply Co., Ltd.Inventors: Chih-Wei Yang, Shih-Sheng Yang, Hou-Chun Yang
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Publication number: 20240032236Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.Type: ApplicationFiled: November 7, 2022Publication date: January 25, 2024Inventors: Chin-Ting Chen, Chih-Wei Yang, Shu-Cheng Yang, Che-Wei Chang, Wen-Cheng Huang, Chin-Hung Lee, Chih-Wei Chan
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Publication number: 20240006468Abstract: A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.Type: ApplicationFiled: July 28, 2022Publication date: January 4, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang
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Publication number: 20230200509Abstract: A waterproof container is adapted for an electronic device with a touch screen. The waterproof container includes an upper component and a lower component. The upper component includes a first layer, a second layer and a third layer. The second layer is disposed between the first layer and the third layer. A second touched part of the second layer is connected to a first touched part of the first layer by a plurality of first connections. The second touched part of the second layer is connected to a third touched part of the third layer by a plurality of second connections, and the plurality of first connections and the plurality of second connections are staggered relative to each other. The lower component is connected to the upper component. An accommodating space is enclosed by the lower component and the upper component for accommodating the electronic device.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Universal Trim Supply Co., Ltd.Inventors: Chih-Wei Yang, Shih-Sheng Yang, Hou-Chun Yang
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Patent number: 11628979Abstract: A sealing bag includes a bag body and a sealing system including an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protrudes from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly includes a covering component including a first covering portion detachably installed on the elastomeric protruding component in a sliding manner, and a second covering portion pivotally connected to the first covering portion. The second covering portion drives the first covering portion to squeeze the elastomeric protruding component along a lateral direction different from the protruding direction to seal the slit when the first covering portion is installed on the elastomeric protruding component and the second covering portion pivotally engages with the first covering portion.Type: GrantFiled: September 2, 2021Date of Patent: April 18, 2023Assignee: Universal Trim Supply Co., Ltd.Inventors: Chih-Wei Yang, Shih-Sheng Yang, Hou-Chun Yang
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Publication number: 20220392905Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.Type: ApplicationFiled: June 30, 2021Publication date: December 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang, Chang-Chien Wong, Te-Wei Yeh, Sheng-Yuan Hsueh
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Patent number: 11482517Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.Type: GrantFiled: May 16, 2018Date of Patent: October 25, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung
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Patent number: D971744Type: GrantFiled: May 21, 2021Date of Patent: December 6, 2022Assignee: SEALVAX LLCInventor: Chih-Wei Yang
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Patent number: D1033611Type: GrantFiled: January 18, 2022Date of Patent: July 2, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chia-Hung Cheng, Ding-Wei Chiu, Chih-Wei Yang