Patents by Inventor Chih-Wei Yang

Chih-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057259
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Publication number: 20210057298
    Abstract: A semiconductor package including a semiconductor die, a molding compound and a redistribution structure is provided. The molding compound laterally wraps around the semiconductor die, wherein the molding compound includes a base material and a first filler particle and a second filler particle embedded in the base material. The first filler particle has a first recess located in a top surface of the first filler particle, and the second filler particle has at least one hollow void therein. The redistribution structure is disposed on the semiconductor die and the molding compound, wherein the redistribution structure has a polymer dielectric layer. The polymer dielectric layer includes a body portion and a first protruding portion protruding from the body portion, wherein the body portion is in contact with the base material and the top surface of the first filler particle, and the first protruding portion fits with the first recess of the first filler particle.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Da Tsai, Ching-Hua Hsieh, Chih-Wei Lin, Tsai-Tsung Tsai, Sheng-Chieh Yang, Chia-Min Lin
  • Publication number: 20210050350
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20210050495
    Abstract: A micro light emitting device display apparatus including a circuit substrate, a plurality of epitaxial structures, a plurality of contact pads and a plurality of light shielding patterns is provided. The plurality of epitaxial structures are dispersedly arranged on the circuit substrate. The plurality of contact pads are disposed between the plurality of epitaxial structures and the circuit substrate. The plurality of epitaxial structures are electrically connected to the circuit substrate via the plurality of contact pads respectively. The plurality of light shielding patterns and the plurality of contact pads are alternately arranged on the circuit substrate, and each of the light shielding patterns is connected between two adjacent contact pads without overlapping with the contact pads and is adapted to block light with a wavelength ranging from 150 nm to 400 nm from penetrating through. A method of fabricating the micro light emitting device display apparatus is also provided.
    Type: Application
    Filed: December 11, 2019
    Publication date: February 18, 2021
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Shiang-Ning Yang, Chih-Ling Wu, Yi-Min Su, Bo-Wei Wu
  • Patent number: 10920008
    Abstract: A thermal-curable resin composition is provided. The thermal-curable resin composition comprises: (A) a thermal-curable resin component, which comprises: (a1) bismaleimide resin; (a2) cyanate ester resin; and (a3) epoxy resin, wherein the cyanate ester resin (a2) and the epoxy resin (a3) are respectively in an amount ranging from 50 parts by weight to 150 parts by weight and from 24 parts by weight to 51 parts by weight per 100 parts by weight of the bismaleimide resin (a1); and (B) a filler, wherein the filler (B) is in an amount ranging from 40 parts by weight to 55 parts by weight per 100 parts by weight of the dry weight of the resin composition; and wherein the resin composition has a dynamic viscosity of not higher than 800 Pa·s after being brought into a semi-cured state (B-stage), and the resin composition has a dissipation factor (Df) of not higher than 0.006 at 10 GHz after being cured completely.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN UNION TECHNOLOGY CORPORATION
    Inventors: Ju-Ming Huang, Chen-Hua Yu, Chang-Chien Yang, Guan-Syun Tseng, Chih-Wei Liao
  • Patent number: 10914618
    Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 9, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Sih-Han Li, Chih-Sheng Lin, Ya-Wen Yang, Kuan-Wei Chen, Shyh-Shyuan Sheu
  • Patent number: 10912948
    Abstract: The present invention provides a composite intelligent biological phototherapy device including a base structure, a plurality of white light fluorescent tubes arranged side by side on the base structure, a plurality of LEDs disposed between the white light fluorescent tubes, a housing having an opening and configured to accommodate the base structure and the white light fluorescent tubes and the LEDs thereon, a light-transmittable plate disposed on the housing corresponding to the opening, and an control module configured to respectively control the white light fluorescent tubes and the LEDs. The base structure includes a plurality of sections, and each of the sections has a first surface facing the light-transmittable plate. The white light fluorescent tubes and the LEDs are provided on the first surfaces, and the sections are bent relative to each other so an angle between the first surfaces of adjacent sections is less than 180 degrees.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 9, 2021
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Yi-Cheng Lin, Hsin-Yi Tsai, Min-Wei Hung, Kuo-Cheng Huang, Hsin-Su Yu, Chiou-Lian Lai, Chung-Yao Hsu, Chao-Hung Cheng, Li-Wei Kuo, Hung-Che Chiang, Chih-Yi Yang
  • Publication number: 20210028311
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Publication number: 20210020816
    Abstract: A semiconductor structure includes a substrate, a plurality of micro semiconductor devices and a fixing structure. The micro semiconductor devices are disposed on the substrate. The fixing structure is disposed between the substrate and the micro semiconductor devices. The fixing structure includes a plurality of conductive layers and a plurality of supporting layers. The conductive layers are disposed on the lower surfaces of the micro semiconductor devices. The supporting layers are connected to the conductive layers and the substrate. The material of each of the conductive layers is different from the material of each of the supporting layers.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 21, 2021
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Shiang-Ning YANG, Chih-Ling WU, Yi-Min SU, Bo-Wei WU
  • Patent number: 10895641
    Abstract: A proximity sensing device which is disposed under the OLED panel and has an emitting module and a receiving module, is provided. The emitting module can emit an invisible light which has a peak wavelength not less than 1000 nm. The receiving module is disposed adjacent to the emitting module and can receive a reflecting light from the reflected invisible light. Therefore, the invisible light passing through the OLED panel will not cause a bright spot on the panel.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: January 19, 2021
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Shih-Wen Lai, Yi-Ting Huang, Jing-Hong Lai, Chih-Hao Hsu, Chia-Wei Yang, Chih-Min Lin, Chieh-Yu Kang, Kuang-Mao Lu, Jian-Hong Fan
  • Patent number: 10896882
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes bonding a portion of an inactive surface of an electronic component to a thermal conductive layer of a heat dissipating element, encapsulating the electronic component and the thermal conductive layer with an encapsulant, and forming a circuit structure on the encapsulant and electrically connecting the circuit structure to the electronic component. Since the heat dissipating element is bonded to the electronic component through the thermal conductive layer, the heat dissipating effect of the electronic package is improved.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: PHOENIX & CORPORATION
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Chih-Kuai Yang
  • Patent number: 10888028
    Abstract: An apparatus for dynamic thermal control is provided. The apparatus includes a fan module with multiple fan units, a deflection member configured to direct airflow received from the fan module, and a system component. The apparatus also includes a chassis management controller (CMC). The CMC is coupled to the fan module, deflection member, and the system component. The CMC is configured to dynamically control the deflection member to direct airflow from the fan module to the system component by accounting for at least one environmental element within the apparatus.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 5, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventor: Chih-Wei Yang
  • Patent number: 10878162
    Abstract: A method of designing a layout includes generating first routing tracks assigned to a first color group, generating second routing tracks assigned to a second color group, wherein a first routing track of the first routing tracks is between adjacent second routing tracks of the second routing tracks, and specifying a color stitching region connecting a selected first routing track of the first routing tracks with a selected second routing track of the second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10872978
    Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Wei Yang, Chih-Chang Hung, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10868135
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 10867998
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20200388616
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20200375491
    Abstract: A heartbeat analyzing method and a heartbeat analyzing system are provided. The heartbeat analyzing method includes: sensing a user using a wearable device and acquiring a physiological signal record; performing a dispersion calculation to the physiological signal record using the wearable device and generating a Poincaré plot of the physiological signal record; and inputting the Poincaré plot into a heart rhythm classifier model and determining a heartbeat classification of the user based on personal health data of the user.
    Type: Application
    Filed: May 15, 2020
    Publication date: December 3, 2020
    Applicants: KURA Care LLC, KURA Med Inc.
    Inventors: Kai-Chieh Yang, Ming-Tse Tsai, Minjun Chen, Chih-Wei Chiu, Alvin Hsu, Ka Tin Hui
  • Publication number: 20200381053
    Abstract: An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 3, 2020
    Inventors: Guan-Wei WU, Yao-Wen CHANG, Chih-Chieh CHENG, I-Chen YANG
  • Publication number: 20200373401
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang