Patents by Inventor Chih-Wei Yang

Chih-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310630
    Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
  • Patent number: 11450673
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • Patent number: 11444080
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20220271209
    Abstract: A semiconductor structure includes a substrate, a plurality of micro semiconductor devices and a fixing structure. The micro semiconductor devices are disposed on the substrate. The fixing structure is disposed between the substrate and the micro semiconductor devices. The fixing structure includes a plurality of conductive layers and a plurality of supporting layers. The conductive layers are disposed on the lower surfaces of the micro semiconductor devices. The supporting layers are connected to the conductive layers and the substrate. The material of each of the conductive layers is different from the material of each of the supporting layers.
    Type: Application
    Filed: May 12, 2022
    Publication date: August 25, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Shiang-Ning YANG, Chih-Ling WU, Yi-Min SU, Bo-Wei WU
  • Patent number: 11417511
    Abstract: A method for drying a wafer at room temperature includes a cleaning step, a reacting step and a pressure releasing step. The cleaning step includes putting a processing workpiece into a cleaning solvent. The reacting step includes putting the processing workpiece along with the cleaning solvent into a reaction chamber, implanting a supercritical fluid into the reaction chamber, and increasing a pressure of the reaction chamber to dissolve the cleaning solvent in the supercritical fluid. A critical temperature of the supercritical fluid is below room temperature. The pressure releasing step includes releasing the pressure of the reaction chamber and discharging the supercritical fluid together with the cleaning solvent out of the reaction chamber, after completely dissolving the cleaning solvent in the supercritical fluid.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 16, 2022
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Chih-Cheng Yang, Wen-Chung Chen, Chuan-Wei Kuo, Pei-Yu Wu, Chun-Chu Lin
  • Patent number: 11411100
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin, Choh Fei Yeap
  • Publication number: 20220238768
    Abstract: A display apparatus including a circuit substrate, a plurality of light-emitting elements, an optical film, and an adhesive layer is provided. These light-emitting elements are electrically bonded to the circuit substrate. The optical film overlaps the light-emitting elements. The light-emitting elements are disposed between the optical film and the circuit substrate. The adhesive layer is disposed between the optical film and the circuit substrate, and connects the light-emitting elements and the optical film. A cavity is provided between the light-emitting elements, the circuit substrate, and the adhesive layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: July 28, 2022
    Applicant: Au Optronics Corporation
    Inventors: Chih-Wei Chien, Chih-Hsiang Yang, Shau-Yu Tsai, Cheng-Chuan Chen, Chih-Ling Hsueh
  • Patent number: 11397302
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: July 26, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11393831
    Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
  • Publication number: 20220223733
    Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Chun-Lung Chang, Chih-Wen Hsiung, Kun-Huang Yu, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220223464
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220223634
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20220225493
    Abstract: An electronic device is provided, in which an antenna module for receiving and transmitting radiation signals is disposed on a mounting surface of a circuit board, and an inner layer of the circuit board is formed with a ground surface to arrange a strip-shaped ground circuit along the edges of the ground surface so that the ground circuit occupies at most 50% of the area of the ground surface to improve antenna radiation efficiency.
    Type: Application
    Filed: September 2, 2021
    Publication date: July 14, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ming-Fan Tsai, Chih-Wei Chen, Chien-Cheng Lin, Chao-Ya Yang, Chia-Yang Chen
  • Publication number: 20220216201
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20220208989
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11319115
    Abstract: A sealing bag includes a bag body and a sealing system. The sealing system includes an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protruding from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly is for detachably engaging with the elastomeric protruding component. The covering assembly squeezes the elastomeric protruding component along the protruding direction and a lateral direction different from the protruding direction to seal the slit when the covering assembly engages with the elastomeric protruding component. Such mechanism can ensure nothing goes in or comes out when the slit is sealed. Therefore, the present invention has enhanced reliability.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Universal Trim Supply Co., Ltd.
    Inventors: Chih-Wei Yang, Shih-Sheng Yang, Hou-Chun Yang
  • Publication number: 20210394966
    Abstract: A sealing bag includes a bag body and a sealing system including an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protrudes from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly includes a covering component including a first covering portion detachably installed on the elastomeric protruding component in a sliding manner, and a second covering portion pivotally connected to the first covering portion. The second covering portion drives the first covering portion to squeeze the elastomeric protruding component along a lateral direction different from the protruding direction to seal the slit when the first covering portion is installed on the elastomeric protruding component and the second covering portion pivotally engages with the first covering portion.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Applicant: Universal Trim Supply Co., Ltd.
    Inventors: Chih-Wei Yang, Shih-Sheng Yang, Hou-Chun Yang
  • Patent number: 11205710
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Publication number: 20210300632
    Abstract: A sealing bag includes a bag body and a sealing system. The sealing system includes an elastomeric protruding component and a covering assembly. The elastomeric protruding component is disposed on the bag body and protruding from the bag body along a protruding direction. A slit penetrates through the elastomeric protruding component along the protruding direction and is communicated with an inner space of the bag body. The covering assembly is for detachably engaging with the elastomeric protruding component. The covering assembly squeezes the elastomeric protruding component along the protruding direction and a lateral direction different from the protruding direction to seal the slit when the covering assembly engages with the elastomeric protruding component. Such mechanism can ensure nothing goes in or comes out when the slit is sealed. Therefore, the present invention has enhanced reliability.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: Chih-Wei Yang, Shih-Sheng Yang, Hou-Chun Yang
  • Publication number: 20210173457
    Abstract: An electronic device operating in standby mode is provided. The electronic device includes a power supply unit, a cooling device coupled to the power supply unit, at least one electronic component cooled by the cooling device, and a controller coupled to the cooling device. The controller is operable to periodically monitor power data and the temperature of the at least one electronic component in standby mode. The controller is also operable to regulate power supplied to the cooling device based on the monitored power data and the temperature of the at least one electronic component.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 10, 2021
    Inventors: Yi-Chieh CHEN, Yueh-Chang WU, Jen-Mao CHEN, Chih-Wei YANG